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    • 63. 发明申请
    • CURRENT COMPENSATION CIRCUIT, METHOD AND OPERATIONAL AMPLIFIER
    • 电流补偿电路,方法和运算放大器
    • US20140218115A1
    • 2014-08-07
    • US14173647
    • 2014-02-05
    • Lei HuangNa Meng
    • Lei HuangNa Meng
    • H02M3/04H03F1/30H03F3/45
    • H03F3/45071H03F3/45183H03F3/45744
    • Disclosed is a current compensation circuit. During calibration of a compensation current, a digital control circuit delivers a digital signal with values varying over time to a current compensation array, the current compensation array outputs different amounts of compensation current based on the digital signal with values varying over time, the digital control circuit latches a value of the digital signal, which results in a best compensation current, based on influences of the different amounts of compensation current on a parameter to be calibrated, to complete the calibration. Upon and after completion of the calibration, the digital control circuit continuously delivers the digital signal with the latched value to the current compensation array, and the current compensation array outputs the best compensation current based on the digital signal with the latched value.
    • 公开了一种电流补偿电路。 在校正补偿电流期间,数字控制电路将具有随时间变化的值的数字信号传递到电流补偿阵列,电流补偿阵列基于具有随时间变化的值的数字信号输出不同量的补偿电流,数字控制 电路锁存数字信号的值,根据补偿电流的不同量对待校准的参数的影响,产生最佳的补偿电流,以完成校准。 在完成校准之后,数字控制电路将具有锁存值的数字信号连续地传送到电流补偿阵列,并且电流补偿阵列基于具有锁存值的数字信号输出最佳补偿电流。
    • 64. 发明授权
    • Maximum voltage selection circuit and method and sub-selection circuit
    • 最大电压选择电路及方法及子选择电路
    • US08773168B2
    • 2014-07-08
    • US13913719
    • 2013-06-10
    • Lei Huang
    • Lei Huang
    • H03K5/153
    • G01R19/04G01R19/0038
    • A maximum voltage selection circuit and method and a sub-selection circuit are provided. The maximum voltage selection circuit includes a peripheral signal circuit and a selection circuit with N channels of input voltages. The peripheral signal circuit provides an operating mode signal and a reference voltage to the selection circuit including N sub-selection circuits coupled to the N channels of input voltages respectively. A sub-selection circuit determines its operating mode according to the operating mode signal. In the operating mode, when an input voltage of a sub-selection circuit is larger than the reference voltage, the sub-selection circuit sets itself to the output enable state and sets other sub-selection circuits to the output disable state, and outputs its input voltage as a maximum voltage through a PMOS.
    • 提供最大电压选择电路和方法以及子选择电路。 最大电压选择电路包括外围信号电路和具有N个输入电压通道的选择电路。 外围信号电路向选择电路提供工作模式信号和参考电压,该选择电路包括分别与N个通道的输入电压耦合的N个子选择电路。 子选择电路根据工作模式信号确定其工作模式。 在操作模式中,当子选择电路的输入电压大于参考电压时,子选择电路将其自身设置为输出使能状态,并将其他子选择电路设置为输出禁止状态,并输出其 输入电压作为通过PMOS的最大电压。
    • 65. 发明申请
    • DELAY TIME ADJUSTING CIRCUIT, METHOD, AND INTEGRATED CIRCUIT
    • 延迟时间调整电路,方法和集成电路
    • US20140167830A1
    • 2014-06-19
    • US14103078
    • 2013-12-11
    • Weiming SunAlvan LamLei HuangEmma WangPeng Zhu
    • Weiming SunAlvan LamLei HuangEmma WangPeng Zhu
    • H03K5/13
    • H03K5/131
    • A delay time adjusting circuit is described, in which a reference signal circuit generates at least one reference signal to an A/D conversion circuit, an input signal circuit generates an input signal to the A/D conversion circuit, the A/D conversion circuit compares the input signal with the at least one reference signal to output a digital signal to a digital logic chip, and the digital logic chip determines a delay time based on the digital signal. In this way, the delay time can be determined digitally, and an adjusting accuracy of the delay time can be increased; and also, the delay time can be adjusted through changing the level of the input signal, thus reducing circuit losses and costs
    • 描述了延迟时间调节电路,其中参考信号电路产生至少一个参考信号到A / D转换电路,输入信号电路产生一个到A / D转换电路的输入信号,A / D转换电路 将输入信号与至少一个参考信号进行比较,以将数字信号输出到数字逻辑芯片,并且数字逻辑芯片基于数字信号确定延迟时间。 以这种方式,可以数字地确定延迟时间,并且可以增加延迟时间的调整精度; 也可以通过改变输入信号的电平来调整延迟时间,从而减少电路损耗和成本
    • 68. 发明授权
    • Power-on-reset circuit and reset method
    • 上电复位电路和复位方法
    • US08547147B2
    • 2013-10-01
    • US13459117
    • 2012-04-28
    • Lei Huang
    • Lei Huang
    • H03L7/00
    • H03K17/223G06F1/24
    • Apparatus and methods for a power-on-reset (POR) circuit are provided. In an example, a (POR) circuit can include a self-bias module configured to provide a reference voltage, a feedback module configured to provide a feedback voltage, a comparison module configured to compare the feedback voltage to the reference voltage and to provide an output signal, an inverter configured to couple the output of the comparison module to an enable input of the self-bias module, and a switch module coupled to the inverter, wherein the switch module and the inverter are configured to disabled the self bias module when the feedback voltage exceeds the reference voltage.
    • 提供了上电复位(POR)电路的装置和方法。 在一个示例中,(POR)电路可以包括被配置为提供参考电压的自偏压模块,被配置为提供反馈电压的反馈模块,被配置为将反馈电压与参考电压进行比较的比较模块, 输出信号,被配置为将所述比较模块的输出耦合到所述自偏压模块的使能输入的反相器以及耦合到所述逆变器的开关模块,其中所述开关模块和所述逆变器被配置为当所述开关模块和所述逆变器被禁用时, 反馈电压超过参考电压。