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61. 发明授权

US07833853B2 Method of defining gate structure height for semiconductor devices 有权
标题翻译：定义半导体器件栅极结构高度的方法
公开(公告)号：US07833853B2
公开(公告)日：2010-11-16
申请号：US12339483
申请日：2008-12-19
申请人： Ryan Chia-Jen Chen , Yih-Ann Lin , Joseph Lin , Jr Jung Lin , Yu Chao Lin , Chao-Cheng Chen , Kuo-Tai Huang
发明人： Ryan Chia-Jen Chen , Yih-Ann Lin , Joseph Lin , Jr Jung Lin , Yu Chao Lin , Chao-Cheng Chen , Kuo-Tai Huang
IPC分类号： H01L21/28
CPC分类号： H01L29/7848 , H01L21/28079 , H01L21/28088 , H01L21/28123 , H01L29/165 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/6659 , H01L29/66636
摘要： Provided is a method of semiconductor fabrication including process steps allowing for defining and/or modifying a gate structure height during the fabrication process. The gate structure height may be modified (e.g., decreased) at one or more stages during the fabrication by etching a portion of a polysilicon layer included in the gate structure. The method includes forming a coating layer on the substrate and overlying the gate structure. The coating layer is etched back to expose a portion of the gate structure. The gate structure (e.g., polysilicon) is etched back to decrease the height of the gate structure.
摘要翻译：提供了一种半导体制造方法，包括允许在制造过程期间限定和/或修改栅极结构高度的工艺步骤。栅极结构高度可以在制造期间的一个或多个阶段被修改（例如减小），通过蚀刻包括在栅极结构中的多晶硅层的一部分。该方法包括在衬底上形成覆盖层并覆盖栅极结构。将涂层回蚀刻以露出栅极结构的一部分。蚀刻栅极结构（例如，多晶硅）以降低栅极结构的高度。

62. 发明申请

US20100068876A1 METHODS OF FABRICATING HIGH-K METAL GATE DEVICES 有权
标题翻译：制造高K金属栅极器件的方法
公开(公告)号：US20100068876A1
公开(公告)日：2010-03-18
申请号：US12405965
申请日：2009-03-17
申请人： Yih-Ann Lin , Ryan Chia-Jen Chen , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen , Jr Jung Lin , Yu Chao Lin
发明人： Yih-Ann Lin , Ryan Chia-Jen Chen , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen , Jr Jung Lin , Yu Chao Lin
IPC分类号： H01L21/28
CPC分类号： H01L21/823828 , H01L21/3221 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.
摘要翻译：公开了制造具有高k /金属栅极特征的半导体器件的方法。在一些情况下，公开了制造具有高k /金属栅极特征的半导体器件的方法，其防止或减少非高k /金属栅极晶片和生产工具的高k /金属栅极污染。在一些实施例中，该方法包括在衬底的前侧上的半导体衬底上形成界面层; 在界面层上形成高k电介质层和覆盖层; 在高k和覆盖层上形成金属层; 在所述金属层上形成多晶硅层; 以及在所述衬底的背面上在所述半导体衬底上形成介电层。

63. 发明申请

US20100052067A1 METHOD OF FABRICATING DUAL HIGH-K METAL GATES FOR MOS DEVICES 有权
标题翻译：用于制造MOS器件的双高K金属栅的方法
公开(公告)号：US20100052067A1
公开(公告)日：2010-03-04
申请号：US12424739
申请日：2009-04-16
申请人： Peng-Fu Hsu , Kang-Cheng Lin , Kuo-Tai Huang
发明人： Peng-Fu Hsu , Kang-Cheng Lin , Kuo-Tai Huang
IPC分类号： H01L27/092 , H01L21/8234
CPC分类号： H01L27/092 , H01L21/823842 , H01L29/49 , H01L29/51
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，在第一区域的高k电介质层上形成覆盖层，形成第一金属层在第一区域中的覆盖层和第二区域中的高k电介质之上，然后在第一区域中形成第一栅极堆叠，在第二区域中形成第二栅极叠层，保护第一栅极叠层中的第一金属层，同时对所述第二栅极堆叠中的所述第一金属层进行处理工艺，以及在所述第一栅极堆叠中的所述第一金属层上方以及所述第二栅极堆叠中经处理的第一金属层之上形成第二金属层。

64. 发明申请

US20100052063A1 METHOD TO IMPROVE DIELECTRIC QUALITY IN HIGH-K METAL GATE TECHNOLOGY 有权
标题翻译：在高K金属门技术中提高介电质量的方法
公开(公告)号：US20100052063A1
公开(公告)日：2010-03-04
申请号：US12338787
申请日：2008-12-18
申请人： Yuri Masuoka , Peng-Fu Hsu , Huan-Tsung Huang , Kuo-Tai Huang , Carlos H. Diaz , Yong-Tian Hou
发明人： Yuri Masuoka , Peng-Fu Hsu , Huan-Tsung Huang , Kuo-Tai Huang , Carlos H. Diaz , Yong-Tian Hou
IPC分类号： H01L25/11 , H01L21/4763 , H01L29/78
CPC分类号： H01L29/4925 , H01L21/28061 , H01L21/28185 , H01L21/28194 , H01L21/823842 , H01L29/513 , H01L29/517
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region. The first gate stack includes the high-k dielectric layer, the first capping layer, the layer containing Si, and the metal layer and the second gate stack includes the high-k dielectric layer, the second capping layer, the layer containing Si, and the metal layer.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括提供具有第一有源区和第二有源区的半导体衬底，提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，形成第一覆盖层和第二覆盖层覆盖在高k电介质层上，覆盖第一区域的第一覆盖层和覆盖第二区域的第二封盖层，在第一和第二覆盖层上形成含有硅（Si）的层，形成金属层所述层包含Si，并且在所述第一区域上形成第一栅极堆叠，并且在所述第二有源区域上形成第二栅极堆叠。第一栅极堆叠包括高k电介质层，第一覆盖层，含有Si的层，金属层和第二栅极堆叠包括高k电介质层，第二覆盖层，含有Si的层和金属层。

65. 发明申请

US20100048010A1 SEMICONDUCTOR DEVICE GATE STRUCTURE INCLUDING A GETTERING LAYER 有权
标题翻译：半导体器件门结构包括入门层
公开(公告)号：US20100048010A1
公开(公告)日：2010-02-25
申请号：US12257165
申请日：2008-10-23
申请人： Chien-Hao Chen , Yong-Tian Hou , Peng-Fu Hsu , Kuo-Tai Huang , Donald Y. Chao , Cheng-Lung Hung
发明人： Chien-Hao Chen , Yong-Tian Hou , Peng-Fu Hsu , Kuo-Tai Huang , Donald Y. Chao , Cheng-Lung Hung
IPC分类号： H01L21/28
CPC分类号： H01L21/28518 , H01L21/28185 , H01L21/3221 , H01L29/49 , H01L29/51 , H01L29/513
摘要： A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth.
摘要翻译：提供了一种方法，其允许通过减小栅极结构中的界面层的厚度来维持期望的等效氧化物厚度（EOT）。在基板上形成界面层，在界面层上形成栅极电介质层，例如高k栅极电介质。在覆盖界面层的基板上形成吸气层。吸气层可用于从界面层吸收氧气，使得界面层厚度减少和/或限制生长。

66. 发明申请

US20060172554A1 METHOD OF FORMING GATE DIELECTRIC LAYER 有权
标题翻译：形成栅介质层的方法
公开(公告)号：US20060172554A1
公开(公告)日：2006-08-03
申请号：US10906008
申请日：2005-01-31
申请人： Yu-Ren Wang , Ying-Wei Yen , Liyuan Cheng , Kuo-Tai Huang
发明人： Yu-Ren Wang , Ying-Wei Yen , Liyuan Cheng , Kuo-Tai Huang
IPC分类号： H01L21/00 , H01L21/31 , H01L21/469
CPC分类号： H01L21/0214 , H01L21/02332 , H01L21/0234 , H01L21/28202 , H01L21/3144 , H01L29/518
摘要： A method for forming a gate dielectric layer is described. A silicon oxide layer is formed on a semiconductor substrate. Then, a first and a second nitrogen doping processes are performed in sequence to the silicon oxide layer using plasma comprising inert gas and gaseous nitrogen to form a gate dielectric layer. The first nitrogen doping process is performed at a lower power, a lower pressure and a higher inert gas to nitrogen gas ratio than those at the second nitrogen doping process. The combination of the deeper nitrogen distribution of the first nitrogen doping process and the shallower nitrogen distribution of the second nitrogen doping process produces a flatter total nitrogen distribution profile so that leakage current from electron tunneling through the gate dielectric layer can be reduced.
摘要翻译：描述了形成栅介质层的方法。在半导体衬底上形成氧化硅层。然后，使用包含惰性气体和气态氮的等离子体，依次对氧化硅层进行第一和第二氮掺杂工艺以形成栅极电介质层。第一氮掺杂过程在低功率，低压和高惰性气体与氮气比之下进行，与第二氮掺杂过程相比。第一氮掺杂过程的较深氮分布和第二氮掺杂过程的较浅氮分布的组合产生更平坦的总氮分布分布，从而可以减少来自电介质穿过栅介质层的漏电流。

67. 发明公开

US20240293972A1 PRINT CUTTING MACHINE 审中-公开
公开(公告)号：US20240293972A1
公开(公告)日：2024-09-05
申请号：US18431818
申请日：2024-02-02
申请人： Kuo-Tai Huang
发明人： Kuo-Tai Huang
IPC分类号： B29C64/379 , B33Y40/00
CPC分类号： B29C64/379 , B33Y40/00
摘要： A print cutting machine includes a main body, a moving unit, a cutting unit, a receiving unit, and a workpiece unit. The main body is provided with a receiving space, a first stand, two first slide rails, and two second slide rails. The moving unit is movably mounted on the first stand and includes a second stand, a moving seat, and a fitting seat. The second stand slides on the first stand linearly. The moving seat is moved on the second stand linearly. The fitting seat is mounted on the moving seat. The cutting unit is mounted on the two second slide rails. The receiving unit is received in the receiving space. The workpiece unit is assembled with the moving unit and includes a base, at least one molded portion mounted on the base, and at least one cutout.

68. 发明授权

US08836038B2 CMOS dual metal gate semiconductor device 有权
标题翻译： CMOS双金属栅极半导体器件
公开(公告)号：US08836038B2
公开(公告)日：2014-09-16
申请号：US12883241
申请日：2010-09-16
申请人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee
发明人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/28 , H01L29/66
CPC分类号： H01L21/823842 , H01L21/28044 , H01L21/28088 , H01L21/823835 , H01L29/66545 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层，其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

69. 发明授权

US08450161B2 Method of fabricating a sealing structure for high-k metal gate 有权
标题翻译：制造高k金属栅极密封结构的方法
公开(公告)号：US08450161B2
公开(公告)日：2013-05-28
申请号：US13465551
申请日：2012-05-07
申请人： Chien-Hao Chen , Hao-Ming Lien , Ssu-Yu Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Liang Chen , Chung-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang
发明人： Chien-Hao Chen , Hao-Ming Lien , Ssu-Yu Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Liang Chen , Chung-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang
IPC分类号： H01L21/00 , H01L21/02
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
摘要翻译：本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域密封层的边缘。

70. 发明授权

US08383502B2 Integrated high-K/metal gate in CMOS process flow 有权
标题翻译： CMOS工艺流程中集成的高K /金属栅极
公开(公告)号：US08383502B2
公开(公告)日：2013-02-26
申请号：US13186572
申请日：2011-07-20
申请人： Ryan Chia-Jen Chen , Yih-Ann Lin , Jr Jung Lin , Yi-Shien Mor , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen
发明人： Ryan Chia-Jen Chen , Yih-Ann Lin , Jr Jung Lin , Yi-Shien Mor , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/82385 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L27/0922 , H01L29/0653 , H01L29/401 , H01L29/42372 , H01L29/4966 , H01L29/517
摘要： A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.
摘要翻译：制造半导体器件的方法包括提供具有第一有源区和第二有源区的半导体衬底，在高k电介质层上形成第一金属层，去除第二有源区中的第一金属层的至少一部分在第一有源区的第一金属层上形成第二金属层，在第二有源区的高k电介质层上形成第二金属层，然后在第二金属层上形成硅层。该方法还包括从第一栅极堆叠中去除硅层，从而形成第一沟槽并从第二栅极堆叠形成第二沟槽，并且在第一沟槽中的第二金属层上方形成第三金属层，并在第二金属在第二沟槽中。

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