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61. 发明申请

US20120242990A1 FAULT DETECTION METHOD AND FAULT DETECTION APPARATUS FOR VCSEL 失效
标题翻译： VCSEL的故障检测方法和故障检测装置
公开(公告)号：US20120242990A1
公开(公告)日：2012-09-27
申请号：US13505611
申请日：2010-11-02
申请人： Atsushi Nakata , Chiemi Yamagata , Satoshi Tanaka
发明人： Atsushi Nakata , Chiemi Yamagata , Satoshi Tanaka
IPC分类号： G01J3/28
CPC分类号： G01J1/4257 , H01S5/0021 , H01S5/18311
摘要： Proposed is a technique for detecting a damaged VCSEL in a short time and at low cost. It shows the light emission spectrum of a multi-mode VCSEL before an ESD damage, and the light emission spectrum which shows several peaks corresponding to the structure of the active layer (MQW) and the upper and lower reflectors (DBR) is obtained. On the other hand, when the VCSEL which has an ESD damage has a damage in the active layer, the light emission spectrum which shows fewer peaks than the original number of peaks is obtained. Accordingly, the light spectrum analyzer analyzes the light emission spectrum, and it is determined that ESD damage has occurred when the number of peaks is equal to or smaller than a predetermined number, e.g., two peaks.
摘要翻译：提出了一种在短时间内以低成本检测损坏的VCSEL的技术。它示出了ESD损伤之前的多模VCSEL的发光光谱，并且获得了与活性层（MQW）和上反射器（DBR）的结构相对应的几个峰的发光光谱。另一方面，当具有ESD损伤的VCSEL在有源层中具有损伤时，获得比原始峰值数目更少的峰的发光光谱。因此，光谱分析仪分析发光光谱，并且当峰值数量等于或小于预定数量（例如两个峰值）时，确定已经发生ESD损伤。

62. 再颁专利

USRE43659E1 Method for making a design layout of a semiconductor integrated circuit 有权
标题翻译：制造半导体集成电路的设计布局的方法
公开(公告)号：USRE43659E1
公开(公告)日：2012-09-11
申请号：US12945672
申请日：2010-11-12
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5081
摘要： A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.
摘要翻译：提供了一种用于设计半导体集成电路的方法，其包括基于给定的设计规则压缩半导体集成电路的设计布局以获得压缩图案，预测在用于形成的晶片的表面区域形成的图案所述半导体集成电路基于所述压实图案，通过将所述预测图案与所述压实图案进行比较来获得评价值，判定所述评价值是否满足预定条件，以及当所述评价值被判定为不满足时修改所述设计规则预定条件。

63. 发明申请

US20120198396A1 METHOD OF OPTIMIZING SEMICONDUCTOR DEVICE MANUFACTURING PROCESS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND NON-TRANSITORY COMPUTER READABLE MEDIUM 审中-公开
标题翻译：优化半导体器件制造工艺的方法，制造半导体器件的方法和非电子计算机可读介质
公开(公告)号：US20120198396A1
公开(公告)日：2012-08-02
申请号：US13237854
申请日：2011-09-20
申请人： Masanari KAJIWARA , Sachiko Kobayashi , Satoshi Tanaka , Kazuhiro Takahata , Shigeki Nojima , Toshiya Kotani , Shimon Maeda
发明人： Masanari KAJIWARA , Sachiko Kobayashi , Satoshi Tanaka , Kazuhiro Takahata , Shigeki Nojima , Toshiya Kotani , Shimon Maeda
IPC分类号： G06F17/50
CPC分类号： H01L22/20 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A method of optimizing a semiconductor device manufacturing process according to an embodiment is a method of optimizing a semiconductor device manufacturing process in which a pattern based on circuit design is formed. The method of optimizing a semiconductor device manufacturing process according to the embodiment includes: at the time of calculation of a statistic amount based on a distribution of differences at a plurality of sites between a pattern formed by a first exposing apparatus in a first condition and a pattern formed by a second exposing apparatus in a second condition, calculating the statistic amount after applying weighting to the differences based on information on an electrical characteristic; and repeating the calculating with the second condition being changed, and selecting an condition in which the total sum becomes a minimum or equal to or less than a standard value as an optimized condition of the second exposing apparatus.
摘要翻译：根据实施例的优化半导体器件制造工艺的方法是优化其中形成基于电路设计的图案的半导体器件制造工艺的方法。根据实施例的半导体器件制造方法的优化方法包括：在基于在第一状态下由第一曝光装置形成的图案与第一状态之间的多个位置处的差异的分布的统计量的计算时，在第二状态下由第二曝光装置形成的图案，基于关于电特性的信息对所述差进行加权计算后的统计量; 并重复进行第二条件的计算，并且选择总和变为最小或等于或小于标准值的条件作为第二曝光装置的优化条件。

64. 发明申请

US20120173896A1 CONTROL DEVICE, IMAGE FORMING APPARATUS, AND CONTROL METHOD 有权
标题翻译：控制装置，图像形成装置和控制方法
公开(公告)号：US20120173896A1
公开(公告)日：2012-07-05
申请号：US13326479
申请日：2011-12-15
申请人： Satoshi Tanaka
发明人： Satoshi Tanaka
IPC分类号： G06F1/26
CPC分类号： G03G15/5004 , H04N1/00217 , H04N1/00896 , H04N1/00904 , H04N1/00928 , H04N1/32593 , H04N2201/0036 , H04N2201/0039 , H04N2201/0094
摘要： A power supply circuit receives power from a power supply and supplies the power to loads including a main controller and a first sub-controller performing response action through a network when the supply of power to the main controller is blocked and the image forming apparatus is connected to the network. A second sub-controller controls the blocking of the supply of power to the main controller. The sub-controller determines whether to block the supply of power to the main controller, determines a connection state of the image forming apparatus to the network when the first determination unit determines to block the supply of power, blocks the supply of power to the first sub-control unit according to the determination result, and detects a factor for resuming the supply of power to the main controller and a factor for blocking the supply of power to all or a part of the loads.
摘要翻译：电源电路从电源接收电力，并且当向主控制器的供电被阻止并且图像形成装置被连接时，通过网络向包括主控制器和执行响应动作的第一子控制器的负载供电到网络。第二个子控制器控制对主控制器供电的阻塞。子控制器确定是否阻止对主控制器的供电，当第一确定单元确定阻止电力供应时，确定图像形成设备到网络的连接状态，阻止向第一子控制单元，并且检测恢复向主控制器供电的因素以及阻止向全部或一部分负载供电的因素。

65. 发明申请

US20120145679A1 PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD 有权
标题翻译：等离子体加工设备和等离子体处理方法
公开(公告)号：US20120145679A1
公开(公告)日：2012-06-14
申请号：US13403588
申请日：2012-02-23
申请人： Naoki Matsumoto , Chishio Koshimizu , Yoshinobu Hayakawa , Hidetoshi Hanaoka , Manabu Iwata , Satoshi Tanaka
发明人： Naoki Matsumoto , Chishio Koshimizu , Yoshinobu Hayakawa , Hidetoshi Hanaoka , Manabu Iwata , Satoshi Tanaka
IPC分类号： B23K9/00
CPC分类号： H01J37/32165 , H01J37/32082
摘要： In a plasma processing apparatus, a first electrode is attached to a grounded evacuable processing chamber via an insulating material or a space and a second electrode disposed in parallel with the first electrode spaced apart therefrom in the processing chamber, the second electrode supporting a target substrate to face the first electrode. A first radio frequency power supply unit applies a first radio frequency power of a first frequency to the second electrode, and a second radio frequency power supply unit applies a second radio frequency power of a second frequency lower than the first frequency to the second electrode. Further, a processing gas supply unit supplies a processing gas to a processing space formed by the first and the second electrode and a sidewall of the processing chamber. Moreover, an inductor electrically is connected between the first electrode and a ground potential.
摘要翻译：在等离子体处理装置中，第一电极经由绝缘材料或空间连接到接地的可抽出处理室，并且在处理室中与与其间隔开的第一电极平行设置的第二电极，第二电极支撑目标衬底面对第一个电极。第一射频电源单元向第二电极施加第一频率的第一射频功率，第二射频电源单元将第二频率低于第一频率的第二射频功率施加到第二电极。此外，处理气体供给单元将处理气体供给到由第一和第二电极以及处理室的侧壁形成的处理空间。此外，电感器电连接在第一电极和地电位之间。

66. 发明申请

US20120069876A1 TRANSCEIVER 失效
标题翻译：收发器
公开(公告)号：US20120069876A1
公开(公告)日：2012-03-22
申请号：US13238249
申请日：2011-09-21
申请人： Hiroshi Kamizuma , Satoshi Tanaka , Taizo Yamawaki , Yukinori Akamine , Koji Maeda
发明人： Hiroshi Kamizuma , Satoshi Tanaka , Taizo Yamawaki , Yukinori Akamine , Koji Maeda
IPC分类号： H04B1/38
CPC分类号： H04B1/0082
摘要： A transceiver includes an oscillator and a plurality of communication blocks. Each of the communication blocks includes frequency dividers and mixers. Frequency dividing number of the frequency divider included in one communication block is set to an even-numbered integer, and transmission local signals supplied from the frequency dividers to the mixer become quadrature signals having a phase difference of 90 degrees. The frequency dividing number of another frequency divider in the another communication block is set to a non-integer, and communication local signals supplied from the frequency divider to the mixers become non-quadrature signals having a phase difference at a predetermined offset angle from 90 degrees. The transceiver further includes a converting unit for giving a compensation offset amount having almost the same absolute value and having a polarity opposite to that of the offset angle to communication analog signals related to the mixer of the another communication block.
摘要翻译：收发机包括振荡器和多个通信块。每个通信块包括分频器和混频器。包含在一个通信块中的分频器的分频数被设置为偶数整数，并且从分频器提供给混频器的发送本地信号变为具有90度相位差的正交信号。将另一通信块中的另一个分频器的分频数设置为非整数，并且从分频器提供给混频器的通信本地信号变为具有从90度的预定偏移角的相位差的非正交信号。收发器还包括转换单元，用于给出具有与相对于另一通信块的混频器相关的通信模拟信号具有几乎相同的绝对值并且具有与偏移角的极性相反的极性的补偿偏移量。

67. 发明授权

US08138445B2 Plasma processing apparatus and plasma processing method 有权
标题翻译：等离子体处理装置和等离子体处理方法
公开(公告)号：US08138445B2
公开(公告)日：2012-03-20
申请号：US11694153
申请日：2007-03-30
申请人： Naoki Matsumoto , Chishio Koshimizu , Yoshinobu Hayakawa , Hidetoshi Hanaoka , Manabu Iwata , Satoshi Tanaka
发明人： Naoki Matsumoto , Chishio Koshimizu , Yoshinobu Hayakawa , Hidetoshi Hanaoka , Manabu Iwata , Satoshi Tanaka
IPC分类号： B23K10/00
CPC分类号： H01J37/32165 , H01J37/32082
摘要： In a plasma processing apparatus, a first electrode is attached to a grounded evacuable processing chamber via an insulating material or a space and a second electrode disposed in parallel with the first electrode spaced apart therefrom in the processing chamber, the second electrode supporting a target substrate to face the first electrode. A first radio frequency power supply unit applies a first radio frequency power of a first frequency to the second electrode, and a second radio frequency power supply unit applies a second radio frequency power of a second frequency lower than the first frequency to the second electrode. Further, a processing gas supply unit supplies a processing gas to a processing space formed by the first and the second electrode and a sidewall of the processing chamber. Moreover, an inductor electrically is connected between the first electrode and a ground potential.
摘要翻译：在等离子体处理装置中，第一电极经由绝缘材料或空间连接到接地的可抽出处理室，并且在处理室中与与其间隔开的第一电极平行设置的第二电极，第二电极支撑目标衬底面对第一个电极。第一射频电源单元向第二电极施加第一频率的第一射频功率，第二射频电源单元将第二频率低于第一频率的第二射频功率施加到第二电极。此外，处理气体供给单元将处理气体供给到由第一和第二电极以及处理室的侧壁形成的处理空间。此外，电感器电连接在第一电极和地电位之间。

68. 发明授权

US08078996B2 Method and system for correcting a mask pattern design 失效
标题翻译：用于校正掩模图案设计的方法和系统
公开(公告)号：US08078996B2
公开(公告)日：2011-12-13
申请号：US12457751
申请日：2009-06-19
申请人： Kyoko Izuha , Shigeki Nojima , Toshiya Kotani , Satoshi Tanaka
发明人： Kyoko Izuha , Shigeki Nojima , Toshiya Kotani , Satoshi Tanaka
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36
摘要： A pattern verification method includes preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, and computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges. The positional displacement is a displacement between first point and the evaluation point. The method further includes computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.
摘要翻译：模式验证方法包括在衬底上制备期望图案和形成期望图案的掩模图案，在期望图案的边缘上限定至少一个评估点，限定至少一个过程参数以计算所转移/形成的图案，定义针对每个处理参数的参考值和可变范围，并且计算与评估点相对应的每个第一点的位置偏移，使用校正掩模图案计算的第一点和通过改变处理参数获得的参数值的多个组合在可变范围内或在相应的可变范围内。位置偏移是第一点与评价点之间的位移。该方法还包括计算每个评估点的位置偏移的统计量，并根据统计信息输出修改掩模图案的信息。

69. 发明授权

US08064331B2 Transmitting apparatus and method for maintaining learned information 有权
标题翻译：用于维护学习信息的发送装置和方法
公开(公告)号：US08064331B2
公开(公告)日：2011-11-22
申请号：US11442221
申请日：2006-05-30
申请人： Masayuki Tanaka , Satoshi Tanaka , Yasuhiro Ooba
发明人： Masayuki Tanaka , Satoshi Tanaka , Yasuhiro Ooba
IPC分类号： G01R31/08 , H04L12/28
CPC分类号： H04L67/2823 , H04L67/28 , H04L69/08
摘要： A protocol converting unit stores identification information for identifying a transfer path for data in a second network and a transmission source address specified in a packet in a corresponding manner. A failure detecting unit detects a transfer path in which a failure has occurred in the second network. A dummy-packet transmitting unit obtains a transmission source address corresponding to identification information of the transfer path in which the failure is detected, and transmits a dummy packet in which the obtained transmission source address is specified as the transmission source address to a first network.
摘要翻译：协议转换单元以相应的方式存储用于识别在第二网络中的数据的传送路径和分组中指定的传输源地址的标识信息。故障检测单元检测在第二网络中发生故障的传送路径。虚拟分组发送单元获得与检测到故障的传送路径的识别信息相对应的发送源地址，并将所获得的发送源地址被指定为发送源地址的虚拟分组发送到第一网络。

70. 发明申请

US20110226513A1 ELECTRONIC COMPONENT PACKAGE AND METHOD FOR PRODUCING ELECTRONIC COMPONENT PACKAGE 失效
标题翻译：电子部件组件及其制造方法电子元件封装件
公开(公告)号：US20110226513A1
公开(公告)日：2011-09-22
申请号：US13128338
申请日：2009-11-19
申请人： Toshiaki Chuma , Masayoshi Kondo , Satoshi Tanaka , Kenichi Kanemasa
发明人： Toshiaki Chuma , Masayoshi Kondo , Satoshi Tanaka , Kenichi Kanemasa
IPC分类号： H05K1/09 , H05K3/00 , H05K1/18 , H05K1/02
CPC分类号： H01L24/16 , H01L23/49816 , H01L24/81 , H01L24/97 , H01L2221/68331 , H01L2221/68336 , H01L2224/1134 , H01L2224/131 , H01L2224/13109 , H01L2224/16 , H01L2224/73104 , H01L2224/81192 , H01L2224/81193 , H01L2224/812 , H01L2224/81801 , H01L2224/83192 , H01L2224/97 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/0101 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/15311 , H01L2924/19041 , H01L2924/351 , Y10T29/49124 , H01L2224/81 , H01L2224/13099 , H01L2924/00
摘要： Disclosed is an electronic component package 100 including a circuit board 10, an electronic component 20, and an adhesive layer 30. The circuit board 10 is provided with an electrically-conductive conductor post 16 which is buried in a base member 12, and a solder layer 18 which is provided at the front end 13 of the conductor post 16 while exposed from a surface 121 of the base member 12. An electrode pad 24 having a metal layer 22 mounted thereon is provided on the main surface 26 of the electronic component 20. The adhesive layer 30 contains a flux activating compound, and bonds the surface 121 of the base member 12 and the main surface 26 of the electronic component 20. Then, the metal layer 22 and the solder layer 18 are metal-bonded.
摘要翻译：本发明公开了一种电子部件，其包括一个电路板10，电子部件20和粘合层30的电路基板10上设置有导电性导体柱16，其被埋设在基体构件12，和焊料封装100 其在导体柱16的前端部13设置在从基体部件12具有22个安装在其上的金属层的电极焊盘24的表面121露出的层18设置在电子部件20的主表面26上该粘合剂层30含有焊剂活化化合物，和债券基体部件12和电子部件20的主表面26然后的表面121，该金属层22和焊料层18金属结合。

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