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    • 62. 发明授权
    • Cell controller, battery module and power supply system
    • 电池控制器,电池模块和电源系统
    • US08264204B2
    • 2012-09-11
    • US11971564
    • 2008-01-09
    • Masaki NagaokaAkihiko KudoMutsumi KikuchiKenichiro TsuruTatsumi YamauchiAkihiko Emori
    • Masaki NagaokaAkihiko KudoMutsumi KikuchiKenichiro TsuruTatsumi YamauchiAkihiko Emori
    • H02J7/00
    • H02J7/0016B60L11/1855B60L11/1866B60L11/1879Y02T10/7005Y02T10/7011Y02T10/7061
    • A cell controller with excellent reliability in which noise and soon are suppressed is provided. The cell controller includes, corresponding to the number of cell packs, a plurality of ICs each having a voltage detecting circuit detecting voltages of respective cells of a cell pack in which four cells are connected in series, a switch control circuit controlling conduction and a blocking operation of a plurality of switch elements connected in parallel to the respective cells via capacity adjusting resistors, a LIN1 terminal for inputting control information, a LIN2 terminal for outputting control information, a Vcc terminal and a GND terminal, and a LIN2 terminal of a higher-order IC and a LIN1 terminal of a lower-order IC are connected in a daisy chain. The Vcc terminal of each IC is connected to a positive electrode of a higher-order cell among cells constituting a corresponding cell pack via an inductor L for eliminating noise, and the GND terminal is coupled directly to the Vcc terminal of the lower-order IC. Noise is not superposed on the LIN1, LIN2 terminals.
    • 提供具有良好可靠性的电池控制器,其中噪声很快被抑制。 电池控制器包括对应于电池组数量的多个IC,每个IC具有电压检测电路,该电压检测电路检测其中四个电池串联连接的电池组的各个电池单元的电压,开关控制电路控制导通和阻塞 多个开关元件的操作通过容量调节电阻并联连接到各个单电池,用于输入控制信息的LIN1端子,用于输出控制信息的LIN2端子,Vcc端子和GND端子以及较高的LIN2端子 低阶IC和LIN1端子以菊花链连接。 每个IC的Vcc端子经由用于消除噪声的电感器L连接到构成相应电池组的单电池中的高电压单元的正电极,并且GND端子直接耦合到低位IC的Vcc端子 。 LIN1,LIN2端子不会叠加噪声。
    • 69. 发明授权
    • Semiconductor integrated circuit apparatus
    • 半导体集成电路装置
    • US06590425B2
    • 2003-07-08
    • US09887065
    • 2001-06-25
    • Fumio MurabayashiTatsumi YamauchiTakashi HottaHiromichi Yamada
    • Fumio MurabayashiTatsumi YamauchiTakashi HottaHiromichi Yamada
    • H03K19096
    • H03K19/00338
    • There is disclosed a circuit apparatus which is highly tolerant to noises and operates at a higher speed than a conventional completely complementary static CMOS circuit. To achieve this, the circuit apparatus features a plurality of CMOS static logic circuits which are series-connected and potential setting circuitry which is connected to the output parts of these logic circuits and sets the outputs of the output parts to a low level in synchronization with a clock signal, thus propagating signals by operation of the NMOS circuit. In other words, a signal propagation delay occurs only when the N-type logic block conducts. Therefore, circuit operation is speeded up and &agr; particle noise and noises due to charge redistribution effect or leakage current can be prevented. There is also disclosed a parallel data processing apparatus which features such logic circuitry, the data processing apparatus having both a plurality of data processing units, each having a processor and a memory, and a plurality of hard disks.
    • 公开了一种电路装置,其高度耐受噪声并以比传统的完全互补的静态CMOS电路更高的速度工作。 为了实现这一点,电路装置具有串联连接的多个CMOS静态逻辑电路和连接到这些逻辑电路的输出部分的电位设置电路,并将输出部分的输出与 时钟信号,从而通过NMOS电路的操作传播信号。 换句话说,信号传播延迟仅在N型逻辑块导通时才发生。 因此,可以防止电路操作加剧,并且可以防止由于电荷再分配效应或漏电流引起的α粒子噪声和噪声。 还公开了一种具有这种逻辑电路的并行数据处理装置,数据处理装置具有多个数据处理单元,每个数据处理单元具有处理器和存储器,以及多个硬盘。