专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US5917355A Edge-triggered staticized dynamic flip-flop with conditional shut-off mechanism 失效
标题翻译：具有条件关断机制的边沿触发静态动态触发器
公开(公告)号：US5917355A
公开(公告)日：1999-06-29
申请号：US784282
申请日：1997-01-16
申请人： Edgardo F. Klass
发明人： Edgardo F. Klass
IPC分类号： H03K3/356 , H03K3/286
CPC分类号： H03K3/356121
摘要： A single phase edge-triggered staticized dynamic flip-flop circuit for use with dynamic logic gates includes a dynamic input stage and a static output stage. The dynamic input stage is coupled to receive a data signal and a clock signal. During the precharge phase, the dynamic input stage provides an output signal that is the complement of the data signal. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the evaluation phase, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage. During the evaluation phase, the static output stage outputs the complement of the output signal received from the dynamic input stage.
摘要翻译：用于动态逻辑门的单相边沿触发静态动态触发器电路包括动态输入级和静态输出级。动态输入级被耦合以接收数据信号和时钟信号。在预充电阶段期间，动态输入级提供作为数据信号的补码的输出信号。动态输入级输出信号在预充电阶段被预充电到逻辑高电平。在评估阶段期间，动态输入级产生一个输出信号，该输出信号保持在逻辑高电平，或者从高到低转换，补充数据信号的逻辑电平。静态输出级接收来自动态输入级的输出信号和时钟信号。在预充电阶段期间，静态输出级将触发器输出信号逻辑保持在先前评估阶段的逻辑电平，而与从动态输入级接收的信号无关。在评估阶段，静态输出级输出从动态输入级接收的输出信号的补码。

IPRDB

热门服务

关于我们

友情链接

联系方式