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61. 发明授权

US5268585A Non-volatile memory and method of manufacturing the same 失效
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US5268585A
公开(公告)日：1993-12-07
申请号：US896010
申请日：1992-06-09
申请人： Yoshimitsu Yamauchi
发明人： Yoshimitsu Yamauchi
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L29/423 , H01L29/788 , H01L29/68 , H01L21/265
CPC分类号： H01L27/11519 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7885
摘要： A non-volatile memory comprises an auxiliary gate of polysilicon provided on a Si substrate having a gate insulating film and a field oxidation film; a floating gate which is provided on a side wall of the auxiliary gate lying in an active region with a small piece of a first insulating film interposed between them and which is formed by etchback of useless part of a polysilicon side wall spacer; and a control gate of polysilicon provided at least on the floating gate including a second insulating film interposed between them; the floating gate being formed in self-alignment to the control gate.
摘要翻译：非易失性存储器包括设置在具有栅极绝缘膜和场氧化膜的Si衬底上的多晶硅辅助栅极; 设置在位于有源区域的辅助栅极侧壁上的浮置栅极，其中插入有位于它们之间的第一绝缘膜的小片，并且通过蚀刻多晶硅侧壁间隔物的无用部分形成; 以及至少设置在所述浮置栅极上的多晶硅控制栅极，包括插在其间的第二绝缘膜; 浮动栅极与控制栅极自对准地形成。

62. 发明授权

US5139964A Method for forming isolation region of semiconductor device 失效
标题翻译：形成半导体器件隔离区域的方法
公开(公告)号：US5139964A
公开(公告)日：1992-08-18
申请号：US646203
申请日：1991-01-28
申请人： Shigeo Onishi , Kenichi Tanaka , Yoshimitsu Yamauchi , Keizo Sakiyama
发明人： Shigeo Onishi , Kenichi Tanaka , Yoshimitsu Yamauchi , Keizo Sakiyama
IPC分类号： H01L21/76 , H01L21/308 , H01L21/316 , H01L21/32 , H01L21/762
CPC分类号： H01L21/3085 , H01L21/32 , H01L21/7621 , Y10S438/944
摘要： An improved LOCOS method for forming an isolation region with a higher breakdown voltage and a reduced width in a semiconductor device, comprising the steps of:(a) forming on a silicon substrate a silicon nitride layer having a predetermined pattern and a tapered-slant side wall, between the silicon nitride layer and the silicon substrate being formed a silicon oxide layer,(b) subjecting the silicon substrate to an isotropic etching using the silicon nitride layer as a mask to form a recess on the substrate, the recess extending to and under the side wall of the silicon nitride layer, and(c) forming a channel stopper region by implanting an impurity into the silicon substrate through the recess-formed surface, and thereafter growing and forming a LOCOS layer on the recess-formed surface to obtain an isolation region.
摘要翻译：一种用于在半导体器件中形成具有较高击穿电压和减小的宽度的隔离区域的改进的LOCOS方法，包括以下步骤：（a）在硅衬底上形成具有预定图案和倾斜斜面的氮化硅层在氮化硅层和硅衬底之间形成硅氧化物层，（b）使用氮化硅层作为掩模对硅衬底进行各向同性蚀刻，以在衬底上形成凹部，在氮化硅层的侧壁下方，（c）通过凹陷形成表面向硅衬底中注入杂质形成通道阻挡区域，然后在凹形形成表面上生长并形成LOCOS层以获得隔离区。

63. 发明授权

US5108783A Process for producing semiconductor devices 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5108783A
公开(公告)日：1992-04-28
申请号：US454368
申请日：1989-12-21
申请人： Makoto Tanigawa , Hidehisa Tateoka , Keizo Sakiyama , Shigeo Ohnishi , Yoshimitsu Yamauchi , Kenichi Tanaka
发明人： Makoto Tanigawa , Hidehisa Tateoka , Keizo Sakiyama , Shigeo Ohnishi , Yoshimitsu Yamauchi , Kenichi Tanaka
IPC分类号： H01L21/76 , H01L21/08 , H01L21/74 , H01L21/762 , H01L21/763 , H01L27/08
CPC分类号： H01L21/763 , H01L21/74 , H01L21/76202 , H01L21/76237
摘要： A process for producing a semiconductor device including the steps of:(a) forming a trench in a semiconductor substrate at a portion thereof where an isolating zone is to be formed,(b) doping the substrate with an impurity element from the inner wall thereof defining the trench to form a high-concentration impurity diffused region, and(c) etching the bottom surface of the trench to increase the depth of the trench, thereby separating the impurity diffused region to form the isolating zone,which is useful for the fabrication of semiconductor devices of high integration with low well resistance.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：（a）在半导体衬底的形成隔离区的部分形成沟槽，（b）从其内壁掺杂杂质元素的衬底限定沟槽以形成高浓度杂质扩散区域，以及（c）蚀刻沟槽的底表面以增加沟槽的深度，由此分离杂质扩散区域以形成隔离区，其可用于制造的半导体器件，具有低阱电阻的高集成度。

64. 发明授权

US5075888A Semiconductor memory device having a volatile memory device and a non-volatile memory device 失效
标题翻译：具有易失性存储器件和非易失性存储器件的半导体存储器件
公开(公告)号：US5075888A
公开(公告)日：1991-12-24
申请号：US308854
申请日：1989-02-09
申请人： Yoshimitsu Yamauchi , Kenichi Tanaka , Keizo Sakiyama
发明人： Yoshimitsu Yamauchi , Kenichi Tanaka , Keizo Sakiyama
IPC分类号： G11C11/00 , G11C11/404 , G11C14/00 , G11C11/40
CPC分类号： G11C11/005 , G11C11/404 , G11C14/00
摘要： A semiconductor memory device composed of a DRAM, an EEPROM, a mode switch means for selecting either mode of the DRAM mode and the EEPROM mode, and a transfer means for transferring data stored in the DRAM to the EEPROM and vice versa. The DRAM consists of one transistor and one capacitor, and one of the terminals of the capacitor is electrically isolated.

65. 发明授权

US5063425A Semiconductor memory device with capacitor over non-volatile memory cell gate structure 失效
标题翻译：半导体存储器件具有电容器超过非易失性存储器单元栅极结构
公开(公告)号：US5063425A
公开(公告)日：1991-11-05
申请号：US481179
申请日：1990-02-20
申请人： Yoshimitsu Yamauchi , Keizo Sakiyama
发明人： Yoshimitsu Yamauchi , Keizo Sakiyama
IPC分类号： H01L21/8247 , G11C14/00 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115
摘要： An improved semiconductor memory device combining a volatile semiconductor storage with a nonvolatile semiconductor storage is disclosed. A capacitor for storing data in the volatile semiconductor storage is formed in a stack structure having a accumulation node polysilicon layer held in ohmic contact with the drain area of the nonvolatile semiconductor storage, an insulation film and a capacitor gate sequentially laminated one over the other on the nonvolatile semiconductor storage. The memory cell size can be minimized for high density applications thereof, with a longer data retention time achieved in the volatile semiconductor storage.
摘要翻译：公开了一种将易失性半导体存储器与非易失性半导体存储器组合的改进的半导体存储器件。用于在易失性半导体存储器中存储数据的电容器形成为具有与非易失性半导体存储器的漏极区域保持欧姆接触的累积节点多晶硅层的堆叠结构，相互层叠的绝缘膜和电容器栅极非易失性半导体存储器。对于其高密度应用，存储器单元尺寸可以最小化，在易失性半导体存储器中实现更长的数据保留时间。

66. 发明授权

US08836688B2 Display device 有权
标题翻译：显示设备
公开(公告)号：US08836688B2
公开(公告)日：2014-09-16
申请号：US13522618
申请日：2010-11-19
申请人： Yoshimitsu Yamauchi
发明人： Yoshimitsu Yamauchi
IPC分类号： G09G5/00 , G09G3/36
CPC分类号： G09G3/3648 , G09G3/36 , G09G3/3614 , G09G3/3618 , G09G3/3655 , G09G3/3659 , G09G2300/043 , G09G2300/0465 , G09G2300/0814 , G09G2300/0819 , G09G2300/0852 , G09G2300/0876 , G09G2310/08 , G09G2320/0247 , G09G2320/043 , G09G2330/021
摘要： A display device which can prevent deterioration of a liquid crystal and reduction in display quality at low power consumption without lowering an aperture ratio is provided. An opposite voltage (Vcom) is applied to an opposite electrode (80) of a liquid crystal capacitive element (Clc). One ends of a pixel electrode (20), a first switch circuit (22), a second switch circuit (23), and a first terminal of a second transistor (T2) form an internal node (N1). The other ends of the first switch circuit (22) and the second switch circuit (23) are connected to a source line (SL) and a voltage supply line (VSL), respectively. A control terminal of a first transistor (T1) in the second switch circuit (23), a second terminal of the second transistor (T2), and one end of a boost capacitive element (Cbst) form an output node (N2). The other end of the boost capacitive element (Cbst) and the control terminal of the second transistor (T2) are connected to a boost line (BST) and a reference line (REF), respectively. This configuration makes it possible to perform an action (self-refresh action) to return the absolute value of the voltage between both ends of a display element part to the value at the time of a last writing action without performing a writing action.
摘要翻译：提供一种能够防止液晶劣化并且在低功耗下降低显示质量而不降低开口率的显示装置。将相对电压（Vcom）施加到液晶电容元件（Clc）的相对电极（80）。像素电极（20），第一开关电路（22），第二开关电路（23）和第二晶体管（T2）的第一端子的一端形成内部节点（N1）。第一开关电路（22）和第二开关电路（23）的另一端分别连接到源极线（SL）和电压供给线（VSL）。第二开关电路（23）中的第一晶体管（T1）的控制端子，第二晶体管（T2）的第二端子和升压电容元件（Cbst）的一端形成输出节点（N2）。升压电容元件（Cbst）的另一端和第二晶体管（T2）的控制端分别连接到升压线（BST）和基准线（REF）。该配置使得可以执行动作（自刷新动作），以将显示元件部分的两端之间的电压的绝对值返回到上一次写入动作时的值而不执行写入动作。

67. 发明授权

US08786531B2 Pixel circuit and display device 有权
标题翻译：像素电路和显示设备
公开(公告)号：US08786531B2
公开(公告)日：2014-07-22
申请号：US13635740
申请日：2010-11-19
申请人： Yoshimitsu Yamauchi
发明人： Yoshimitsu Yamauchi
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G02F1/13624 , G09G3/3618 , G09G3/3655 , G09G3/3659 , G09G2300/0861 , G09G2300/0876 , G09G2320/10 , G09G2330/022
摘要： A display device which realizes constant display having multiple tones with low power consumption is provided. A pixel circuit 2 has an internal node N1 holding a pixel data voltage applied to a display element unit 21, a first switch circuit 22 transferring the pixel data voltage supplied from a data signal line SL to the internal node N1 through a series circuit of first and second transistor elements T1 and T2, a second circuit 23 having a third transistor element T3 which communicates between an intermediate node N2 connected with the first and second transistor elements T1 and T2, and a voltage supply line VSL, and a control circuit 24 formed with a series circuit of a fourth transistor element T4 and a first capacitative element C1, holding the pixel data voltage held in the internal node N1 at one end of the first capacitative element C1 through the fourth transistor element T4, and controlling conduction of the third transistor element T3 by a boost voltage applied to the other end of the first capacitative element C1, and the first and second transistor elements T1 and T2 are controlled individually.
摘要翻译：提供实现具有低功耗的多个音调的恒定显示的显示装置。像素电路2具有保持施加到显示元件单元21的像素数据电压的内部节点N1，将数据信号线SL提供的像素数据电压传送到内部节点N1的第一开关电路22通过第一和第二晶体管元件T1和T2，具有连接在与第一和第二晶体管元件T1和T2连接的中间节点N2之间的第三晶体管元件T3和电压供应线VSL的第二电路23和形成的控制电路24 利用第四晶体管元件T4和第一电容元件C1的串联电路，通过第四晶体管元件T4保持保持在第一电容元件C1的一端的内部节点N1中的像素数据电压，并且控制第三晶体管元件T4的导通通过施加到第一电容元件C1的另一端的升压电压，并且第一和第二晶体管元件T1和T2是控制晶体管元件T3 d单独。

68. 发明申请

US20120154365A1 PIXEL CIRCUIT AND DISPLAY DEVICE 有权
标题翻译：像素电路和显示设备
公开(公告)号：US20120154365A1
公开(公告)日：2012-06-21
申请号：US13392893
申请日：2010-05-24
申请人： Yoshimitsu Yamauchi
发明人： Yoshimitsu Yamauchi
IPC分类号： G09G5/00
CPC分类号： G09G3/3659 , G09G2300/0852
摘要： A display device includes liquid crystal capacitor element interposed between a pixel electrode and a counter electrode. The pixel electrode, one terminals of a first switch circuit and a second switch circuit, and a first terminal of a second transistor form an internal node. The other terminals of the first switch circuit is connected to the source line. The other terminal of the second switch circuit is connected to the voltage supply line and is configured by a series circuit of transistors. A control terminal of the transistor, a second terminal of the transistor, and one terminal of a boost capacitor element form an output node. The other terminal of the boost capacitor element, the control terminal of the transistor, and the control terminal of the transistor are connected to a boost line, a reference line, and a selecting line, respectively.
摘要翻译：显示装置包括夹在像素电极和对置电极之间的液晶电容器元件。像素电极，第一开关电路的一个端子和第二开关电路以及第二晶体管的第一端子形成内部节点。第一开关电路的其他端子连接到源极线。第二开关电路的另一个端子连接到电源线，并由晶体管的串联电路构成。晶体管的控制端子，晶体管的第二端子和升压电容器元件的一个端子形成输出节点。升压电容器元件的另一端子，晶体管的控制端子和晶体管的控制端子分别连接到升压线，参考线和选择线。

69. 发明申请

US20120154262A1 Pixel Circuit And Display Device 审中-公开
标题翻译：像素电路和显示设备
公开(公告)号：US20120154262A1
公开(公告)日：2012-06-21
申请号：US13392892
申请日：2010-05-24
申请人： Yoshimitsu Yamauchi
发明人： Yoshimitsu Yamauchi
IPC分类号： G09G3/36
CPC分类号： G09G3/3659 , G09G2300/0852
摘要： A display device which achieves low power consumption without causing an aperture ratio to be lowered is provided. A pixel circuit includes: an internal node which holds a voltage of the pixel data supplied to a display element part; a first switch circuit which transfers the voltage of the pixel data supplied from a data signal line to the internal node through at least a switch element; a second switch circuit which transfers a voltage supplied to a predetermined voltage supply line to the internal node without going through the switch element; and a control circuit which holds a predetermined voltage depending on the voltage of the pixel data held in the internal node, at one end of a first capacitance element and controls connection/disconnection of the second switch circuit.
摘要翻译：提供了一种在不导致开口率降低的情况下实现低功耗的显示装置。像素电路包括：内部节点，其保持提供给显示元件部分的像素数据的电压; 第一开关电路，其通过至少一个开关元件将从数据信号线提供的像素数据的电压传送到内部节点; 第二开关电路，其将提供给预定电源线的电压传送到所述内部节点而不经过所述开关元件; 以及控制电路，其在第一电容元件的一端保持取决于保持在内部节点中的像素数据的电压的预定电压，并且控制第二开关电路的连接/断开。

70. 发明申请

US20050239245A1 Nonvolatile semiconductor memory and method of operating the same 有权
标题翻译：非易失性半导体存储器及其操作方法
公开(公告)号：US20050239245A1
公开(公告)日：2005-10-27
申请号：US11157973
申请日：2005-06-22
申请人： Yoshimitsu Yamauchi
发明人： Yoshimitsu Yamauchi
IPC分类号： G11C16/04 , G11C7/00 , H01L21/8239 , H01L21/8242 , H01L21/8247 , H01L27/105 , H01L27/112 , H01L27/115 , H01L29/76 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115
摘要： A nonvolatile semiconductor memory having a memory cell comprises: a semiconductor substrate having a pair of trenches formed on a surface thereof; first electrodes formed in a pair of trenches through the intervention of a first insulating film, respectively; a second electrode formed on the semiconductor substrate between the trenches through the intervention of a second insulating film; and a third electrode formed on the second electrode through the intervention of a third insulating film.
摘要翻译：具有存储单元的非易失性半导体存储器包括：具有在其表面上形成的一对沟槽的半导体衬底; 分别通过介入第一绝缘膜形成在一对沟槽中的第一电极; 通过介入第二绝缘膜形成在沟槽之间的半导体衬底上的第二电极; 以及通过第三绝缘膜介入形成在第二电极上的第三电极。

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