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    • 62. 发明授权
    • Semiconductor integrated circuit device
    • 半导体集成电路器件
    • US06339344B1
    • 2002-01-15
    • US09497280
    • 2000-02-02
    • Takeshi SakataHitoshi TanakaOsamu NagashimaMasafumi OhiSadayuki Morita
    • Takeshi SakataHitoshi TanakaOsamu NagashimaMasafumi OhiSadayuki Morita
    • H03K190175
    • H03K19/018528
    • Differential amplifier circuits that receive input signals fed through external terminals are served with a first operation voltage and a second operation voltage through a first switching MOSFET and a second switching MOSFET, said first and second switching MOSFETs are turned on by a bias voltage-generating circuit when said input signal is near a central voltage of said first and second operation voltages, control voltages are formed to turn either said first switching MOSFET or said second switching MOSFET on and to turn the other one off to produce a corresponding output signal when the input signal continuously assumes said first voltage or said second voltage for a predetermined period of time, thereby to supply an input signal of a first amplitude corresponding to said first operation voltage and said second operation voltage as well as an input signal of a second amplitude corresponding to a predetermined intermediate voltage between said first operation voltage and said second operation voltage.
    • 接收通过外部端子馈送的输入信号的差分放大器电路通过第一开关MOSFET和第二开关MOSFET被提供第一工作电压和第二工作电压,所述第一和第二开关MOSFET由偏置电压产生电路 当所述输入信号接近所述第一和第二操作电压的中心电压时,形成控制电压以使所述第一开关MOSFET或所述第二开关MOSFET导通,并将另一个断开以产生相应的输出信号,当输入 信号连续地采取所述第一电压或所述第二电压预定的时间段,从而提供对应于所述第一操作电压和所述第二操作电压的第一幅度的输入信号以及对应于所述第一操作电压的第二幅度的输入信号 所述第一操作电压和所述第二操作电压之间的预定中间电压 工作电压。
    • 63. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US06212110B1
    • 2001-04-03
    • US09471504
    • 1999-12-23
    • Tatsuya SakamotoOsamu NagashimaRiichiro Takemura
    • Tatsuya SakamotoOsamu NagashimaRiichiro Takemura
    • G11C700
    • G11C11/4097G11C7/06G11C7/18G11C11/4091
    • Switch MOSFETS are interposed between a sense amplifier disposed in a dynamic RAM and complementary bit lines. After signal voltages were read out by the selecting operations of the word lines from a plurality of dynamic memory cells selected, to the plurality of pairs of complementary bit lines in accordance with their individual storage informations, the switch control signal of the switch MOSFETs is changed from a select level to a predetermined intermediate level. The switch MOSFETs, supplied with the intermediate potential at their gates, are turned ON as a result that sense nodes are set to one level in accordance with the amplifying operations of the sense amplifier. An amplification signal generated by the amplifying operation is transmitted through the column select circuit to input/output lines in response to the column select signal, and the switch control signal is returned from the intermediate potential level to the select level in response to the selecting operation of the column select circuit.
    • 开关MOSFETS插入设置在动态RAM中的读出放大器和互补位线之间。 通过根据所选择的多个动态存储单元的字线的选择操作读出信号电压后,根据其各自的存储信息到多对互补位线,开关MOSFET的开关控制信号被改变 从选择级别到预定中间级别。 在其栅极处提供有中间电位的开关MOSFET被导通,结果是根据读出放大器的放大操作将感测节点设置为一个电平。 通过放大运算产生的放大信号响应于列选择信号而通过列选择电路发送到输入/输出线,并且响应于选择操作将开关控制信号从中间电位电平返回到选择电平 的列选择电路。
    • 64. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US5726930A
    • 1998-03-10
    • US653236
    • 1996-05-24
    • Masatoshi HasegawaKazuhiko KajigayaKan TakeuchiKatsumi MatsunoOsamu Nagashima
    • Masatoshi HasegawaKazuhiko KajigayaKan TakeuchiKatsumi MatsunoOsamu Nagashima
    • G11C14/00G11C11/22G11C11/401G11C11/404H01L21/8242H01L27/10H01L27/108
    • G11C11/22G11C11/404
    • A semiconductor memory device capable of simultaneously providing volatile and non-volatile portions is disclosed having a plurality of memory mats, and a plurality of plate electrodes and a plurality of memory mats each provided in one-to-one correspondence with the memory maps. The memory mats each include a plurality of word lines, a plurality of bit lines and a plurality of memory cells provided at the intersections of the word lines and the bit lines. The memory cells each include an information storage capacitor having a ferroelectric film, and an address selection MOSFET. The information storage capacitor has a pair of electrodes, one of which is connected to the plate electrode that corresponds to the memory mat in which the information storage capacitor is included. A first voltage or a second voltage is selectively applied to each of the plate electrodes according to data held in the memory circuit corresponding to the plate electrode. When the first voltage is applied to the plate electrode, the information storage capacitors connected to the plate electrode are made incapable of polarization reversal irrespective of a binary write signal given to the bit lines. When the second voltage is applied to the plate electrode, the information storage capacitors connected to the plate electrode are made capable of polarization inversion in response to a binary write signal given to the bit lines.
    • 公开了能够同时提供易失性和非易失性部分的半导体存储器件,其具有多个存储器垫,以及多个板电极和多个存储器垫,每个存储垫与存储器映射图一一对应地提供。 存储器垫每个都包括多个字线,多个位线和设置在字线和位线的交点处的多个存储单元。 存储单元各自包括具有铁电膜的信息存储电容器和地址选择MOSFET。 信息存储电容器具有一对电极,其中一个电极连接到对应于包括信息存储电容器的存储器垫的平板电极。 根据与平板电极相对应的存储电路中保存的数据,选择性地向每个平板电极施加第一电压或第二电压。 当第一电压施加到平板电极时,连接到平板电极的信息存储电容器不会产生极化反转,而与给定位线的二进制写入信号无关。 当第二电压施加到平板电极时,连接到平板电极的信息存储电容器响应于给定位线的二进制写入信号而能够进行极化反转。
    • 65. 发明授权
    • Liquid crystal display device
    • 液晶显示装置
    • US08755020B2
    • 2014-06-17
    • US13556259
    • 2012-07-24
    • Osamu Nagashima
    • Osamu Nagashima
    • G02F1/1339
    • G02F1/13394G02F1/1337G02F2001/133388G02F2001/13396
    • A region of the first substrate and the second substrate enclosed by a sealant is a rectangle. The rectangle includes a central region, a pair of first regions between which the central region is interposed in a major-axis direction of the rectangle, a pair of second regions between which the central region is interposed in a minor-axis direction of the rectangle, and a peripheral region that surrounds the central region, the pair of first regions, and the pair of second regions. The spacers are disposed in the central region and the peripheral region except the pair of first regions and the pair of second regions. In the peripheral region, a width from each of the first regions to one long side of the rectangle in an outward direction is larger than a width from one of the second regions to the one long side in the outward direction.
    • 由密封剂包围的第一基板和第二基板的区域是矩形。 矩形包括中心区域,一对第一区域,中心区域在矩形的长轴方向插入中间区域,一对第二区域,中心区域在矩形的短轴方向上插入 以及围绕中心区域,一对第一区域和一对第二区域的周边区域。 间隔物设置在中心区域和除一对第一区域和一对第二区域之外的周边区域。 在周边区域中,沿着向外方向的矩形的每个第一区域到一个长边的宽度大于从向外方向的第二区域中的一个到一个长边侧的宽度。