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61. 发明授权

US06925411B1 Method and apparatus for aligning semiconductor chips using an actively driven vernier 有权
标题翻译：使用主动驱动游标对准半导体芯片的方法和装置
公开(公告)号：US06925411B1
公开(公告)日：2005-08-02
申请号：US10741961
申请日：2003-12-19
申请人： Robert J. Drost , Ivan E. Sutherland
发明人： Robert J. Drost , Ivan E. Sutherland
IPC分类号： G01C17/00 , H01L23/544
CPC分类号： H01L22/34 , H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06527 , H01L2225/06593 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： One embodiment of the present invention provides a system that facilitates measuring an alignment between a first semiconductor die and a second semiconductor die. The system provides a plurality of conductive elements on the first semiconductor die and a plurality of conductive elements on the second semiconductor die. The plurality of conductive elements on the second semiconductor die have a different spacing than the plurality of conductive elements on the first semiconductor die, so that when the plurality of conductive elements on the first semiconductor die overlap the plurality of conductive elements on the second semiconductor die, a vernier alignment structure is created between them. The system also provides a charging mechanism configured to selectively charge each of the plurality of conductive elements on the first semiconductor die, wherein charging a conductive element on the first semiconductor die induces a charge in one or more conductive elements on the second semiconductor die. An amplification mechanism then amplifies the signals induced in the conductive elements on the second semiconductor die. These signals can be analyzed to determine the alignment between the first semiconductor die and the second semiconductor die.
摘要翻译：本发明的一个实施例提供一种便于测量第一半导体管芯和第二半导体管芯之间的对准的系统。该系统在第一半导体管芯上提供多个导电元件，并在第二半导体管芯上提供多个导电元件。第二半导体管芯上的多个导电元件具有与第一半导体管芯上的多个导电元件不同的间隔，使得当第一半导体管芯上的多个导电元件与第二半导体管芯上的多个导电元件重叠时在它们之间创建游标对齐结构。该系统还提供了一种配置成选择性地对第一半导体管芯上的多个导电元件充电的充电机构，其中对第一半导体管芯上的导电元件充电在第二半导体管芯上的一个或多个导电元件中引起电荷。然后，放大机构放大在第二半导体管芯上的导电元件中感应的信号。可以分析这些信号以确定第一半导体管芯和第二半导体管芯之间的对准。

62. 发明授权

US06812046B2 Method and apparatus for electronically aligning capacitively coupled chip pads 有权
标题翻译：用于电子对准电容耦合芯片焊盘的方法和装置
公开(公告)号：US06812046B2
公开(公告)日：2004-11-02
申请号：US10207671
申请日：2002-07-29
申请人： Robert J. Drost , Ivan E. Sutherland , Gregory M. Papadopoulos
发明人： Robert J. Drost , Ivan E. Sutherland , Gregory M. Papadopoulos
IPC分类号： H01L2166
CPC分类号： H04B5/0012 , G06F17/5077 , H01L23/48 , H01L23/544 , H01L2223/54473 , H01L2225/06531 , H01L2924/0002 , H01L2924/0001
摘要： One embodiment of the present invention provides a system that electronically aligns pads on different semiconductor chips to facilitate communication between the semiconductor chips through capacitive coupling. The system operates by measuring an alignment between a first chip and a second chip, wherein the first chip is situated face-to-face with the second chip so that transmitter pads on the first chip are capacitively coupled with receiver pads on the second chip. Next, the system uses the measured alignment to associate transmitter pads on the first chip with proximate receiver pads on the second chip. The system then selectively routes data signals to transmitter pads on the first chip so that the data signals are communicated through capacitive coupling to intended receiver pads in the second chip that are proximate to the transmitter pads.
摘要翻译：本发明的一个实施例提供一种系统，其电子地对准不同半导体芯片上的焊盘，以便于通过电容耦合在半导体芯片之间进行通信。该系统通过测量第一芯片和第二芯片之间的对准来工作，其中第一芯片与第二芯片面对面设置，使得第一芯片上的发射器焊盘与第二芯片上的接收器焊盘电容耦合。接下来，系统使用测量的对准来将第一芯片上的发射器焊盘与第二芯片上的接近焊盘相关联。然后，系统选择性地将数据信号路由到第一芯片上的发射机焊盘，使得数据信号通过电容耦合传递到靠近发射器焊盘的第二芯片中的预期接收器焊盘。

63. 发明授权

US06456136B1 Method and apparatus for latching data within a digital system 有权
标题翻译：用于在数字系统内锁定数据的方法和装置
公开(公告)号：US06456136B1
公开(公告)日：2002-09-24
申请号：US09834772
申请日：2001-04-13
申请人： Ivan E. Sutherland , Scott M. Fairbanks
发明人： Ivan E. Sutherland , Scott M. Fairbanks
IPC分类号： H03K3356
CPC分类号： H03K3/356156 , H03K3/356139
摘要： A latching data system includes a memory element that is configured to store a data value. A latch input is coupled to the memory element, so that changes in the latch input change the data value stored in the memory element without waiting for an assertion of a clock signal. The system also includes a driver circuit that is configured to drive the data value stored in the memory element onto a latch output. The system additionally includes a clocking circuit that is configured to cause the driver circuit to drive the data value stored in the memory element onto the latch output in response to an assertion of the clock signal.
摘要翻译：锁存数据系统包括被配置为存储数据值的存储器元件。锁存器输入耦合到存储器元件，使得锁存器输入中的变化改变存储在存储元件中的数据值，而不用等待时钟信号的断言。该系统还包括被配置为将存储在存储器元件中的数据值驱动到锁存器输出上的驱动器电路。该系统还包括时钟电路，其被配置为响应于时钟信号的断言使驱动器电路将存储在存储器元件中的数据值驱动到锁存器输出上。

64. 发明授权

US06420907B1 Method and apparatus for asynchronously controlling state information within a circuit 有权
标题翻译：用于异步地控制电路内的状态信息的方法和装置
公开(公告)号：US06420907B1
公开(公告)日：2002-07-16
申请号：US09676430
申请日：2000-09-29
申请人： Ivan E. Sutherland , Scott M. Fairbanks , Josephus C. Ebergen
发明人： Ivan E. Sutherland , Scott M. Fairbanks , Josephus C. Ebergen
IPC分类号： H03K19094
CPC分类号： G05B19/045 , G05B2219/23289 , G05B2219/25263 , G05B2219/25306
摘要： One embodiment of the present invention provides a system for asynchronously controlling state information within a circuit. This system includes a first conductor that carries a voltage indicating a state of the circuit, as well as a first drive circuit coupled to the first conductor that is configured to drive the first conductor to a first voltage level to indicate a first state. The system also includes a second drive circuit coupled to the first conductor that is configured to drive the first conductor to a second voltage level to indicate a second state. The system additionally includes a condition input that indicates a condition. The system is configured so that the first drive circuit drives the first conductor to the first voltage level based upon the condition indicated by the condition input. In one embodiment of the present invention, the first drive circuit is additionally configured to drive the first conductor to the first voltage level based upon the state indicated by the voltage carried on the first conductor. In one embodiment of the present invention, the system additionally includes a keeper circuit coupled to the first conductor that is configured to hold the voltage on the first conductor at a stable value, unless the voltage is changed by a drive circuit. In one embodiment of the present invention, the system additionally includes a pulse generation circuit coupled to the first drive circuit, wherein the pulse generation circuit is configured to cause the first drive circuit to drive the first conductor to the first voltage level using a pulse of limited duration.
摘要翻译：本发明的一个实施例提供一种用于异步地控制电路内的状态信息的系统。该系统包括承载指示电路的状态的电压的第一导体以及耦合到第一导体的第一驱动电路，其被配置为将第一导体驱动到第一电压电平以指示第一状态。该系统还包括耦合到第一导体的第二驱动电路，其被配置为将第一导体驱动到第二电压电平以指示第二状态。该系统还包括指示条件的条件输入。该系统被配置为使得第一驱动电路基于条件输入指示的条件将第一导体驱动到第一电压电平。在本发明的一个实施例中，第一驱动电路还被配置为基于由第一导体上承载的电压指示的状态将第一导体驱动到第一电压电平。在本发明的一个实施例中，系统还包括耦合到第一导体的保持器电路，其被配置为将电压保持在第一导体上的稳定值，除非电压被驱动电路改变。在本发明的一个实施例中，系统还包括耦合到第一驱动电路的脉冲发生电路，其中脉冲发生电路被配置为使第一驱动电路使用第一驱动电路的脉冲将第一导体驱动到第一电压电平持续时间有限

65. 发明授权

US06188262B1 Synchronous polyphase clock distribution system 有权
标题翻译：同步多相时钟分配系统
公开(公告)号：US06188262B1
公开(公告)日：2001-02-13
申请号：US09146810
申请日：1998-09-04
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： G06F104
CPC分类号： G06F1/10 , G06F1/06
摘要： A clock distribution system is described for providing synchronous clock signals in as many phases as a designer of a given circuit finds useful. The clock distribution system acknowledges timing constraints of the controlled system, and adjusts the clock phase appropriately to meet the needs of the local data circuits using the clock signals. The clock distribution system includes stages which are coupled to appropriate portions of the datapath and to each other for controlling the datapath and provide information about clock signal timing to each other.
摘要翻译：描述了一种时钟分配系统，用于提供与给定电路的设计者有用的多个相位的同步时钟信号。时钟分配系统确认受控系统的时序约束，并且适当地调整时钟相位以满足使用时钟信号的本地数据电路的需要。时钟分配系统包括耦合到数据路径的适当部分并且彼此相连以控制数据通路并且提供关于时钟信号定时的信息的阶段。

66. 发明授权

US5955898A Selector and decision wait using pass gate XOR 失效
标题翻译：选择器和决定等待使用传输门XOR
公开(公告)号：US5955898A
公开(公告)日：1999-09-21
申请号：US885169
申请日：1997-06-30
申请人： Ivan E. Sutherland , William S. Coates , Jon K. Lexau
发明人： Ivan E. Sutherland , William S. Coates , Jon K. Lexau
IPC分类号： H03K17/693 , H03K19/0948
CPC分类号： H03K17/693
摘要： A logic gate includes a plurality of pass gates forming a double rail pass gate XOR or reversing switch providing the same functionality as a conventional XOR gate. Consequently, the pass gate XOR can substitute for XOR gates in circuits such as a selector circuit and decision wait circuit, but with faster responses and fewer transistors than the conventional XOR gate. Each pass gate includes a P-type and an N-type transistor coupled in parallel. A control input and its complement are coupled to the gates of the transistors to selectively pass signals at the input of the pass gate to its output.
摘要翻译：逻辑门包括形成双轨栅极XOR或反向开关的多个栅极，提供与传统XOR栅极相同的功能。因此，通过门XOR可以在诸如选择器电路和判决等待电路的电路中替代XOR门，但是具有比常规XOR门更快的响应和更少的晶体管。每个通过门包括并联耦合的P型和N型晶体管。控制输入及其补码耦合到晶体管的栅极，以选择性地将通孔的输入端处的信号传递到其输出端。

67. 发明授权

US5838939A Multi-issue/plural counterflow pipeline processor 失效
标题翻译：多重/多个逆流管线处理器
公开(公告)号：US5838939A
公开(公告)日：1998-11-17
申请号：US853970
申请日：1997-05-09
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： G06F9/38 , G06F15/16 , G06F15/80
CPC分类号： G06F9/3867
摘要： A computer system architecture is described for providing increased performance in a counterflow pipeline processor. The system includes an instruction fetching unit, a register file, and a pipeline connected between the instruction fetching unit and the register file. The pipeline is formed from a group of sequential stages. Each stage in the pipeline includes a first instruction register for storing a first instruction, a second instruction register for storing a second instruction, and a first results register for storing results. The instructions are transferred in a first direction from stage to stage, and results are transferred in an opposite direction from stage to stage. The registers for the instructions include an operand field, a first source field for the operand, a second source field for the operand, and a destination field. Each of the fields itself includes a register name, a value, and a validity bit. In operation instructions and results pass each other in the pipeline and the results of execution of the instructions are transferred to the register file and to the results fields. In another approach to providing improved performance plural pipelines are employed, individual ones of which may have multiple instruction registers therein.
摘要翻译：描述了用于在逆流管线处理器中提供增加的性能的计算机系统架构。该系统包括连接在指令提取单元和寄存器文件之间的指令取出单元，寄存器文件和流水线。管道由一组顺序阶段形成。流水线中的每个阶段包括用于存储第一指令的第一指令寄存器，用于存储第二指令的第二指令寄存器和用于存储结果的第一结果寄存器。指令沿着第一方向从阶段转移到阶段，并且结果以相反的方向从阶段转移到阶段。指令的寄存器包括操作数字段，操作数的第一个源字段，操作数的第二个源字段和一个目标字段。每个字段本身都包含一个寄存器名称，一个值和一个有效位。在操作中，指令和结果在流水线中相互通过，指令的执行结果被传送到寄存器文件和结果字段。在提供改进的性能的另一种方法中，采用多个管线，其中单独的管线可以在其中具有多个指令寄存器。

68. 发明授权

US5567110A Robot arm structure 失效
公开(公告)号：US5567110A
公开(公告)日：1996-10-22
申请号：US446009
申请日：1995-05-19
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： B25J18/06 , B25J9/00
CPC分类号： B25J18/06 , Y10T74/20323
摘要： Disclosed is a flexible robot arm structure utilizing an elongate skeletal frame member which can be controlled to assume any of a number of curved shapes as in the performance of automated operations. The arm functions somewhat like the body of a snake or an elephant's trunk. The skeletal frame defines a plurality of similar elemental segments disclosed in the form of disc-like structures as well as turns in a helical loading configuration. The helical form includes interleaved flexible helix members interconnected in a chain-link form. Displacement of sections in the arm is accomplished by the action of two separate mechanisms. A deflection mechanism provides power to flex or curve an arm section while a distribution mechanism distributes the curvature along the length of the arm to seek a smooth, circular curve. Illustrative embodiments use hydraulic actuators integral with the frame; however, equivalents are disclosed. The resulting arm is a highly repetitive, mechanical structure.

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