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61. 发明申请

US20130093471A1 TIME-TO-DIGITAL SYSTEM AND ASSOCIATED FREQUENCY SYNTHESIZER 有权
标题翻译：时间到数字系统和相关的频率合成器
公开(公告)号：US20130093471A1
公开(公告)日：2013-04-18
申请号：US13450242
申请日：2012-04-18
申请人： Yi-Hsien Cho , Robert Bogdan Staszewski
发明人： Yi-Hsien Cho , Robert Bogdan Staszewski
IPC分类号： H03B21/00
CPC分类号： H03L7/081 , G06F1/32 , H03L7/16 , H03L7/18 , H03L2207/50
摘要： A time-to-digital system, such as a frequency synthesizer, includes a power management circuit and a time-to-digital converter (TDC). Said power management circuit is coupled to a frequency reference clock and a variable clock, and arranged to output a delayed frequency reference clock and a single pulse of said variable clock ahead of a transition of said delayed frequency reference clock. Said TDC is coupled to said power management circuit and arranged to produce a digital TDC output.
摘要翻译：诸如频率合成器的时间 - 数字系统包括电源管理电路和时间 - 数字转换器（TDC）。所述功率管理电路耦合到频率参考时钟和可变时钟，并被布置成在所述延迟的频率参考时钟的转变之前输出延迟的频率参考时钟和所述可变时钟的单个脉冲。所述TDC耦合到所述功率管理电路并被布置成产生数字TDC输出。

62. 发明申请

US20120025918A1 APPARATUS AND METHOD FOR CALIBRATING TIMING MISMATCH OF EDGE ROTATOR OPERATING ON MULTIPLE PHASES OF OSCILLATOR 有权
标题翻译：用于校准在多个振荡器相位操作的边缘旋转器的时序误差的装置和方法
公开(公告)号：US20120025918A1
公开(公告)日：2012-02-02
申请号：US13170187
申请日：2011-06-28
申请人： Chi-Hsueh Wang , Robert Bogdan Staszewski
发明人： Chi-Hsueh Wang , Robert Bogdan Staszewski
IPC分类号： H03L7/06
CPC分类号： H03L7/0996
摘要： An exemplary calibration apparatus for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes a capturing block arranged to capture phase error samples, and a calibrating block arranged to adjust timing of said edge rotator according to said phase error samples. An exemplary calibration method for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes the following steps: capturing phase error samples, and adjusting timing of said edge rotator according to said phase error samples.
摘要翻译：用于校准在振荡器的多相上操作的边缘旋转器的定时失配的示例性校准装置包括布置成捕获相位误差采样的捕获块，以及被配置为根据所述相位误差样本调整所述边缘旋转器的定时的校准块。用于校准在振荡器的多相上操作的边缘旋转器的定时失配的示例性校准方法包括以下步骤：捕获相位误差样本，并根据所述相位误差样本调整所述边缘旋转器的定时。

63. 发明授权

US08050375B2 Digital phase locked loop with integer channel mitigation 有权
标题翻译：数字锁相环，整数通道缓解
公开(公告)号：US08050375B2
公开(公告)日：2011-11-01
申请号：US12024881
申请日：2008-02-01
申请人： Robert Bogdan Staszewski , Sudheer K. Vemulapalli , John L. Wallberg , Khurram Waheed
发明人： Robert Bogdan Staszewski , Sudheer K. Vemulapalli , John L. Wallberg , Khurram Waheed
IPC分类号： H03D3/24
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal with a plurality of phases. A switch is coupled to receive the RF clock, and is operative to select one of the plurality of phases. A phase detection circuit is coupled to the switch and is operable to receive a selected phase and to provide digital phase error samples indicative of a time difference between the reference clock and the selected phase.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生具有多个相位的RF时钟信号。耦合开关以接收RF时钟，并且可操作以选择多个相位中的一个。相位检测电路耦合到开关并且可操作以接收所选择的相位并且提供指示参考时钟和所选相位之间的时间差的数字相位误差样本。

64. 发明授权

US07834686B2 Power amplifier 有权
标题翻译：功率放大器
公开(公告)号：US07834686B2
公开(公告)日：2010-11-16
申请号：US12134464
申请日：2008-06-06
申请人： Robert Bogdan Staszewski , See Taur Lee , Dirk Leipold
发明人： Robert Bogdan Staszewski , See Taur Lee , Dirk Leipold
IPC分类号： H03F1/14
CPC分类号： H03F3/189 , H03F3/211 , H03F3/602 , H03F2200/541
摘要： Methods to implement power control in a digital power amplifier are described.
摘要翻译：描述了在数字功率放大器中实现功率控制的方法。

65. 发明申请

US20100283665A1 Mitigation of RF Oscillator Pulling through Adjustable Phase Shifting 审中-公开
标题翻译： RF振荡器通过可调相移的减轻
公开(公告)号：US20100283665A1
公开(公告)日：2010-11-11
申请号：US12435405
申请日：2009-05-05
申请人： Imran Bashir , Robert Bogdan Staszewski , Oren Eliezer , Meng-Chang Lee
发明人： Imran Bashir , Robert Bogdan Staszewski , Oren Eliezer , Meng-Chang Lee
IPC分类号： G01S7/40 , H04M1/00
CPC分类号： H04B1/0475 , H04B15/02
摘要： A digitally controlled mechanism for the minimization of the self-interference caused by an amplitude modulated signal generated within a polar transmitter to the oscillator circuit, where the carrier of that transmitter is created. A digitally controlled delay between the circuit where the signal is generated and the circuit where it is amplitude-modulated allows adjustment of the delay or phase-shift between the aggressing and victim signals. The optimal delay that is to be introduced in the path is determined, and a corresponding control word is generated to arrive at the selected delay/phase-shift.
摘要翻译：一种数字控制的机制，用于最小化在极性发射机内产生的振幅调制信号对振荡器电路产生的自干扰，其中该发射机的载波被创建。产生信号的电路与其被调幅的电路之间的数字控制延迟允许调整侵入信号和受干扰信号之间的延迟或相移。确定要在路径中引入的最佳延迟，并产生相应的控制字以得到所选择的延迟/相移。

66. 发明申请

US20080317187A1 Interpolative All-Digital Phase Locked Loop 有权
标题翻译：插值全数字锁相环
公开(公告)号：US20080317187A1
公开(公告)日：2008-12-25
申请号：US12022931
申请日：2008-01-30
申请人： Khurram Waheed , Robert Bogdan Staszewski , John L. Wallberg , Sudheer K. Vemulapalli
发明人： Khurram Waheed , Robert Bogdan Staszewski , John L. Wallberg , Sudheer K. Vemulapalli
IPC分类号： H04L7/00
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. An interpolator is coupled to the phase detection circuit for performing a sample rate conversion between the reference clock and the clock derived from the RF clock signal.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生RF时钟信号。相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。内插器耦合到相位检测电路，用于执行参考时钟和从RF时钟信号导出的时钟之间的采样率转换。

67. 发明授权

US09385651B2 60 GHz frequency generator incorporating third harmonic boost and extraction 有权
标题翻译：采用三次谐波增压和提取的60 GHz频率发生器
公开(公告)号：US09385651B2
公开(公告)日：2016-07-05
申请号：US14874416
申请日：2015-10-03
申请人： Zhirui Zong , Masoud Babaie , Robert Bogdan Staszewski
发明人： Zhirui Zong , Masoud Babaie , Robert Bogdan Staszewski
IPC分类号： H03B5/12 , H03L7/081 , H03L7/099
CPC分类号： H03B5/1212 , H03B5/1215 , H03B5/1218 , H03B5/1228 , H03B5/124 , H03B5/1265 , H03B5/1281 , H03B5/1293 , H03B5/1296 , H03J2200/10 , H03L7/081 , H03L7/0991 , H03L7/1976
摘要： A novel and useful 60 GHz frequency generator based on a third harmonic extraction technique which improves system level efficiency and performance. The frequency generator employs a third harmonic boosting technique to increase the third harmonic at the output of the oscillator. The oscillator generates both ˜20 GHz fundamental and a significant amount of the third harmonic at ˜60 GHz and avoids the need for a frequency divider operating at 60 GHz. The undesired fundamental harmonic at ˜20 GHz is rejected by the good fundamental harmonic rejection ratio (HRR) inherent in the oscillator buffer stage while the ˜60 GHz component is amplified to the output. The fundamental harmonic is further suppressed by active cancellation by properly combining the two outputs. The oscillator fabricated in 40 nm CMOS exhibits a phase noise of −100 dBc/Hz at 1 MHz offset from a 60 GHz carrier and have a tuning range of 25%.
摘要翻译：一种基于三次谐波提取技术的新颖有用的60 GHz频率发生器，可提高系统级效率和性能。频率发生器采用三次谐波增强技术来增加振荡器输出端的三次谐波。振荡器在〜60 GHz时产生〜20 GHz基波和大量三次谐波，避免了在60 GHz工作的分频器。在〜20GHz的不希望的基波谐波被振荡器缓冲级固有的良好的基波谐波抑制比（HRR）所抵消，而〜60GHz分量被放大到输出。通过正确组合两个输出，通过主动取消进一步抑制基波。以40nm CMOS制造的振荡器在距离60GHz载波的1MHz偏移处具有-100dBc / Hz的相位噪声，并且具有25％的调谐范围。

68. 发明申请

US20160099691A1 Transformer Based Impedance Matching Network And Related Power Amplifier, ADPLL And Transmitter Based Thereon 有权
标题翻译：基于变压器的阻抗匹配网络及相关功率放大器，ADPLL和发射机
公开(公告)号：US20160099691A1
公开(公告)日：2016-04-07
申请号：US14874421
申请日：2015-10-03
申请人： Masoud Babaie , Robert Bogdan Staszewski
发明人： Masoud Babaie , Robert Bogdan Staszewski
IPC分类号： H03F1/56 , H01F27/28 , H03F3/217 , H03F1/02 , H03F3/193 , H03H7/38 , H01F27/29
CPC分类号： H03H7/38 , H01F27/2823 , H01F27/29 , H01Q1/50 , H03F1/0205 , H03F1/565 , H03F3/193 , H03F3/211 , H03F3/2171 , H03F3/2176 , H03F3/245 , H03F2200/318 , H03F2200/451 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2203/21106 , H03F2203/21139 , H03H7/09 , H03H7/40 , H03H7/425 , H03H7/427 , H03H7/48
摘要： A novel and useful transmitter (TX) architecture for ultra-low power (ULP) radios. An all-digital PLL employs a digitally controlled oscillator (DCO) having switching current sources to reduce supply voltage and power consumption without sacrificing phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL after settling to reduce its sampling rate or shut it off entirely during direct DCO data modulation. A switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency. The transmitter has been realized in 28 nm CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy.
摘要翻译：一种用于超低功耗（ULP）无线电的新颖有用的发射机（TX）架构。全数字PLL采用具有开关电流源的数字控制振荡器（DCO），以降低电源电压和功耗，而不会牺牲相位噪声和启动裕度。它还降低了1 / f噪声，允许ADPLL在稳定后降低采样率或在直接DCO数据调制期间完全关闭它。开关功率放大器在E / F2类中工作时集成了其匹配网络，以最大限度地提高其效率。发射机已经在28nm CMOS中实现，并且满足所有金属密度和其他制造规则。它消耗3.6 mW / 5.5 mW，同时在蓝牙低功耗中提供0 dBm / 3 dBm的射频功率。

69. 发明申请

US20160099685A1 60 GHz Wideband Class E/F2 Power Amplifier 有权
标题翻译： 60 GHz宽带E / F2功率放大器
公开(公告)号：US20160099685A1
公开(公告)日：2016-04-07
申请号：US14874427
申请日：2015-10-03
申请人： Masoud Babaie , Robert Bogdan Staszewski
发明人： Masoud Babaie , Robert Bogdan Staszewski
IPC分类号： H03F1/02 , H03H7/38 , H03F3/217 , H03F3/193 , H03F3/21 , H01F27/28 , H03F1/56
CPC分类号： H03H7/38 , H01F27/2823 , H01F27/29 , H01Q1/50 , H03F1/0205 , H03F1/565 , H03F3/193 , H03F3/211 , H03F3/2171 , H03F3/2176 , H03F3/245 , H03F2200/318 , H03F2200/451 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2203/21106 , H03F2203/21139 , H03H7/09 , H03H7/40 , H03H7/425 , H03H7/427 , H03H7/48
摘要： A novel and useful fully integrated switched-mode wideband 60 GHz power amplifier architecture. Using an appropriate second-harmonic termination of its output matching network, the required systematic peak current of the final stage is reduced such that the PA functions as a class-E/F2 switched-mode PA at saturation. In addition, low/moderate magnetic coupling factor transformers in the intermediate stages enable the PA to reach a high power added efficiency (PAE) and bandwidth product. Transformers of low/moderate coupling are also utilized in the preliminary stages of the PA to improve the overall bandwidth. In addition, the PA exploits the different behavior of the output impedance matching network for differential mode (DM) and common mode (CM) excitations. The PA is also stabilized against the combination of DM and CM oscillation modes. The PA also provides a technique to stabilize transformer-based mm-wave amplifiers against various modes of undesired oscillations.
摘要翻译：一种新颖有用的全集成开关模式宽带60 GHz功率放大器架构。使用其输出匹配网络的适当的二次谐波终端，减少最终级所需的系统峰值电流，使得PA在饱和时用作E类/ F2开关模式PA。此外，中等阶段的低/中等磁耦合因子变压器使PA能够达到高功率附加效率（PAE）和带宽乘积。低/中耦合变压器也用于PA的初级阶段，以提高整体带宽。此外，PA利用差分模式（DM）和共模（CM）激励的输出阻抗匹配网络的不同行为。 PA还针对DM和CM振荡模式的组合进行了稳定。 PA还提供了一种技术来稳定基于变压器的毫米波放大器，以抵抗各种不希望的振荡模式。

70. 发明授权

US08804874B2 Polar transmitter having digital processing block used for adjusting frequency modulating signal for frequency deviation of frequency modulated clock and related method thereof 有权
标题翻译：具有数字处理块的极性发射机，用于调频频调制频率的频率调制信号及其相关方法
公开(公告)号：US08804874B2
公开(公告)日：2014-08-12
申请号：US13612796
申请日：2012-09-12
申请人： Chi-Hsueh Wang , Kai-Peng Kao , Robert Bogdan Staszewski
发明人： Chi-Hsueh Wang , Kai-Peng Kao , Robert Bogdan Staszewski
IPC分类号： H03C3/00
CPC分类号： H03C5/00 , H04L7/002 , H04L7/0331
摘要： A polar transmitter includes a frequency modulating path, a clock divider and a digital processing block. The frequency modulating path is arranged for generating a frequency modulated clock in response to a frequency modulating signal. The clock divider is coupled to the frequency modulated clock, and arranged for generating a down-divided clock. The digital processing block is coupled to the down-divided clock, and arranged for generating the frequency modulating signal, wherein the frequency modulating signal is adjusted for frequency deviation of the frequency modulated clock. A method for polar transmission includes: generating a frequency modulated clock in response to a frequency modulating signal; dividing a frequency of said frequency modulated clock to generate a down-divided clock; and generating said frequency modulating signal according to said down-divided clock, wherein said frequency modulating signal is adjusted for frequency deviation of said frequency modulated clock.
摘要翻译：极性发射机包括频率调制路径，时钟分频器和数字处理模块。频率调制路径被布置成响应于频率调制信号而产生调频时钟。时钟分频器耦合到频率调制时钟，并且被布置用于产生分频时钟。数字处理块耦合到分频时钟，并且被配置为产生频率调制信号，其中调频信号针对频率调制时钟的频率偏差。一种用于极性传输的方法包括：响应于频率调制信号产生调频时钟; 将所述调频时钟的频率除以产生下降时钟; 以及根据所述分频时钟产生所述频率调制信号，其中调节所述频率调制信号以调节所述频率调制时钟的频率偏差。

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