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61. 发明授权

US08775906B2 Efficient storage of meta-bits within a system memory 失效
公开(公告)号：US08775906B2
公开(公告)日：2014-07-08
申请号：US13611909
申请日：2012-09-12
申请人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
发明人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
IPC分类号： G11C29/42 , G06F11/10 , G11C29/54 , G11C29/04
CPC分类号： G06F11/1076 , G06F11/1064 , G06F12/0815 , G06F12/0895 , G11C2029/0411
摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.

62. 发明申请

US20130151929A1 Efficient Storage of Meta-Bits Within a System Memory 有权
标题翻译：系统内存中元位的高效存储
公开(公告)号：US20130151929A1
公开(公告)日：2013-06-13
申请号：US13313364
申请日：2011-12-07
申请人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
发明人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
IPC分类号： G06F11/16 , G06F12/08
CPC分类号： G06F11/1076 , G06F11/1064 , G06F12/0815 , G06F12/0895 , G11C2029/0411
摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.
摘要翻译：提供了用于在系统存储器内有效存储元位的机制。这些机制将L / G位和SUE位组合以形成元位。机制然后在第一个数据周期上确定高速缓存行的本地/全局状态。这些机制将数据转发到请求的高速缓存，并且请求高速缓存可以基于高速缓存行的本地/全局状态全局重新发出请求。这些机制然后在数据的第二个或随后的周期中确定高速缓存行的特殊的不可校正错误状态。机制执行错误处理，而不管请求是否在全球重新发布。

63. 发明授权

US07930610B2 System and method for power reduction through power aware latch weighting of complex sub-circuits 有权
标题翻译：通过复杂子电路的功率感知锁存器加权降低功耗的系统和方法
公开(公告)号：US07930610B2
公开(公告)日：2011-04-19
申请号：US12206781
申请日：2008-09-09
申请人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, Jr.
发明人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, Jr.
IPC分类号： G01R31/28
CPC分类号： G01R31/318536
摘要： A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logical description of identified sub-circuits. A don't-care analysis module couples to the circuit analysis module identifies absolute don't-care latches associated with the identified sub-circuits. A sub-circuit exception module couples to the circuit analysis module and selects weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit. The sub-circuit exception module stores the selected weighted input values for the sub-circuit and associates the selected weighted input values with the logical description.
摘要翻译：一种系统包括被配置为分析待测器件（DUT）的电路分析模块，该DUT包括在扫描链中耦合在一起的多个锁存器。电路分析模块分析DUT内的子电路的DUT，并识别所识别的子电路的逻辑描述。不需要的分析模块耦合到电路分析模块，识别与所识别的子电路相关的绝对不需要的锁存器。子电路异常模块耦合到电路分析模块，并且基于所识别的绝对不需要的锁存器和所识别的子电路的逻辑描述来选择所识别的子电路的加权输入值。子电路异常模块存储用于子电路的选择的加权输入值，并将所选择的加权输入值与逻辑描述相关联。

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