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61. 发明授权

US07889552B2 Non-volatile semiconductor device 失效
标题翻译：非易失性半导体器件
公开(公告)号：US07889552B2
公开(公告)日：2011-02-15
申请号：US12068409
申请日：2008-02-06
申请人： Jae-chul Park , Jae-woong Hyun , Young-soo Park , Sun-il Kim
发明人： Jae-chul Park , Jae-woong Hyun , Young-soo Park , Sun-il Kim
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor device according to example embodiments may include a plurality of memory cells on a semiconductor substrate and at least one selection transistor on the semiconductor substrate, wherein the at least one selection transistor may be disposed at a different level from the plurality of memory cells. The at least one selection transistor may be connected to a data line and/or a power source line via a first contact and/or a third contact, respectively. The at least one selection transistor may be connected to the plurality of memory cells via a second contact and/or a fourth contact. The active layer of the at least one selection transistor may contain an oxide. Accordingly, the nonvolatile semiconductor device according to example embodiments may include a selection transistor having a reduced size.
摘要翻译：根据示例实施例的非易失性半导体器件可以包括半导体衬底上的多个存储单元和半导体衬底上的至少一个选择晶体管，其中所述至少一个选择晶体管可以设置在与所述多个存储单元不同的电平。所述至少一个选择晶体管可以分别经由第一触点和/或第三触点连接到数据线和/或电源线。所述至少一个选择晶体管可以经由第二触点和/或第四触点连接到所述多个存储单元。所述至少一个选择晶体管的有源层可以含有氧化物。因此，根据示例性实施例的非易失性半导体器件可以包括具有减小的尺寸的选择晶体管。

62. 发明申请

US20100283048A1 CMOS image sensor and method of manufacturing the same 有权
标题翻译： CMOS图像传感器及其制造方法
公开(公告)号：US20100283048A1
公开(公告)日：2010-11-11
申请号：US12591909
申请日：2009-12-04
申请人： Sung-ho Park , I-hun Song , Wook Lee , Sang-wook Kim , Sun-il Kim , Jae-chul Park
发明人： Sung-ho Park , I-hun Song , Wook Lee , Sang-wook Kim , Sun-il Kim , Jae-chul Park
IPC分类号： H01L31/032
CPC分类号： H01L27/14636 , H01L27/1225 , H01L27/14609 , H01L27/14612 , H01L27/14641 , H01L27/14645 , H01L27/14689
摘要： Provided is a complementary metal oxide semiconductor (CMOS) image sensor having a structure capable of increasing areas of photodiodes in unit pixels and expanding light receiving areas of the photodiodes. In the CMOS image sensor, transfer transistors may be formed on the photodiode, and reset transistors, source follower transistors, and selection transistors may be formed on a layer on which the transfer transistors are not formed. In such a CMOS image sensor, the areas of the photodiodes may be increased in unit pixels so that a size of the unit pixels may be reduced and sensitivity of the pixel may be improved.
摘要翻译：提供了具有能够增加单位像素中的光电二极管的面积并扩大光电二极管的光接收面积的结构的互补金属氧化物半导体（CMOS）图像传感器。在CMOS图像传感器中，可以在光电二极管上形成传输晶体管，并且可以在不形成传输晶体管的层上形成复位晶体管，源极跟随器晶体管和选择晶体管。在这样的CMOS图像传感器中，可以以单位像素增加光电二极管的面积，从而可以减小单位像素的尺寸，并且可以提高像素的灵敏度。

63. 发明申请

US20090003062A1 Non-volatile semiconductor device 失效
标题翻译：非易失性半导体器件
公开(公告)号：US20090003062A1
公开(公告)日：2009-01-01
申请号：US12068409
申请日：2008-02-06
申请人： Jae-chul Park , Jae-woong Hyun , Young-soo Park , Sun-il Kim
发明人： Jae-chul Park , Jae-woong Hyun , Young-soo Park , Sun-il Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor device according to example embodiments may include a plurality of memory cells on a semiconductor substrate and at least one selection transistor on the semiconductor substrate, wherein the at least one selection transistor may be disposed at a different level from the plurality of memory cells. The at least one selection transistor may be connected to a data line and/or a power source line via a first contact and/or a third contact, respectively. The at least one selection transistor may be connected to the plurality of memory cells via a second contact and/or a fourth contact. The active layer of the at least one selection transistor may contain an oxide. Accordingly, the nonvolatile semiconductor device according to example embodiments may include a selection transistor having a reduced size.
摘要翻译：根据示例性实施例的非易失性半导体器件可以包括半导体衬底上的多个存储单元和半导体衬底上的至少一个选择晶体管，其中所述至少一个选择晶体管可以设置在与所述多个存储单元不同的电平。所述至少一个选择晶体管可以分别经由第一触点和/或第三触点连接到数据线和/或电源线。所述至少一个选择晶体管可以经由第二触点和/或第四触点连接到所述多个存储单元。所述至少一个选择晶体管的有源层可以含有氧化物。因此，根据示例性实施例的非易失性半导体器件可以包括具有减小的尺寸的选择晶体管。

64. 发明授权

US08003419B2 Method of manufacturing light emitting device 有权
标题翻译：制造发光器件的方法
公开(公告)号：US08003419B2
公开(公告)日：2011-08-23
申请号：US12458900
申请日：2009-07-27
申请人： Kyoung-kook Kim , Su-hee Chae , Young-soo Park , Taek Kim , Moon-seung Yang , Hyung-su Jeong , Jae-chul Park , Jun-youn Kim
发明人： Kyoung-kook Kim , Su-hee Chae , Young-soo Park , Taek Kim , Moon-seung Yang , Hyung-su Jeong , Jae-chul Park , Jun-youn Kim
IPC分类号： H01L21/00
CPC分类号： H01L33/0079 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method of manufacturing a light emitting device from a large-area bonding wafer by using a wafer bonding method using. The method may include forming a plurality of semiconductor layers, each having an active region for emitting light, on a plurality of growth substrates. The method may also include arranging the plurality of growth substrates on which the semiconductor layers are formed on one bonding substrate and simultaneously processing each of the semiconductor layers formed on each of the growth substrates through subsequent processes. The bonding wafer may be formed of a material that reduces or prevents bending or warping due to a difference of thermal expansion coefficients between a wafer material, such as sapphire, and a bonding wafer. According to the above method, because a plurality of wafers may be processed by one process, mass production of LEDs may be possible which may reduce manufacturing costs.
摘要翻译：提供了一种使用晶片接合方法从大面积接合晶片制造发光器件的方法。该方法可以包括在多个生长衬底上形成多个半导体层，每个半导体层具有发射光的有源区。该方法还可以包括在其上形成半导体层的多个生长衬底布置在一个接合衬底上，并且通过后续处理同时处理在每个生长衬底上形成的每个半导体层。接合晶片可以由减少或防止由于晶片材料（例如蓝宝石）和接合晶片之间的热膨胀系数的差异而导致的弯曲或翘曲的材料形成。根据上述方法，由于可以通过一个处理来处理多个晶片，因此大量生产LED可能会降低制造成本。

65. 发明授权

US07847287B2 Inverter, logic circuit including an inverter and methods of fabricating the same 有权
标题翻译：逆变器，包括逆变器的逻辑电路及其制造方法
公开(公告)号：US07847287B2
公开(公告)日：2010-12-07
申请号：US12232854
申请日：2008-09-25
申请人： Sang-wook Kim , Young-soo Park , Jae-chul Park
发明人： Sang-wook Kim , Young-soo Park , Jae-chul Park
IPC分类号： H01L29/12 , H01L23/62
CPC分类号： H01L21/823462 , H01L21/84 , H01L27/0883
摘要： An inverter, a logic circuit including the inverter and method of fabricating the same are provided. The inverter includes a load transistor of a depletion mode, and a driving transistor of an enhancement mode, which is connected to the load transistor. The load transistor may have a first oxide layer as a first channel layer. The driving transistor may have a second oxide layer as a second channel layer.
摘要翻译：提供了一种逆变器，包括逆变器的逻辑电路及其制造方法。逆变器包括耗尽模式的负载晶体管和连接到负载晶体管的增强模式的驱动晶体管。负载晶体管可以具有作为第一沟道层的第一氧化物层。驱动晶体管可以具有作为第二沟道层的第二氧化物层。

66. 发明申请

US20090196084A1 Memory chip array 有权
标题翻译：内存芯片阵列
公开(公告)号：US20090196084A1
公开(公告)日：2009-08-06
申请号：US12213121
申请日：2008-06-16
申请人： Jae-chul Park , Ki-won Kwon , Chung-jung Kim , Sang-wook Kim , Sul-il Kim
发明人： Jae-chul Park , Ki-won Kwon , Chung-jung Kim , Sang-wook Kim , Sul-il Kim
IPC分类号： G11C5/02 , G11C8/00
CPC分类号： G11C5/025 , G11C8/10
摘要： Provided is a memory chip array comprising a plurality of cell arrays and at least one predecoder commonly connected to the plurality of cell arrays, wherein the memory chip array promotes an efficient arrangement structure of the memory chip array and is minimized in area.
摘要翻译：提供了一种存储器芯片阵列，其包括多个单元阵列和至少一个共同连接到多个单元阵列的预解码器，其中该存储器芯片阵列促进该存储器芯片阵列的有效布置结构并且在区域中被最小化。

67. 发明授权

US08614442B2 Thin film transistor and method of forming the same 有权
标题翻译：薄膜晶体管及其形成方法
公开(公告)号：US08614442B2
公开(公告)日：2013-12-24
申请号：US12929818
申请日：2011-02-17
申请人： Jae-chul Park , Young-soo Park , Sun-Il Kim
发明人： Jae-chul Park , Young-soo Park , Sun-Il Kim
IPC分类号： H01L29/10
CPC分类号： H01L29/7869 , H01L29/78609
摘要： A thin film transistor (TFT) may include a channel layer, a source electrode, a drain electrode, a protective layer, a gate electrode, and/or a gate insulating layer. The channel layer may include an oxide semiconductor material. The source electrode and the drain electrode may face each other on the channel layer. The protective layer may be under the source electrode and the drain electrode and/or may cover the channel layer. The gate electrode may be configured to apply an electric field to the channel layer. The gate insulating layer may be interposed between the gate electrode and the channel layer.
摘要翻译：薄膜晶体管（TFT）可以包括沟道层，源电极，漏电极，保护层，栅电极和/或栅极绝缘层。沟道层可以包括氧化物半导体材料。源电极和漏电极可以在沟道层上彼此面对。保护层可以在源极和漏极之下，和/或可以覆盖沟道层。栅电极可以被配置为向沟道层施加电场。栅极绝缘层可以插入在栅电极和沟道层之间。

68. 发明授权

US08558323B2 Thin film transistors having multi-layer channel 有权
标题翻译：具有多层通道的薄膜晶体管
公开(公告)号：US08558323B2
公开(公告)日：2013-10-15
申请号：US12923472
申请日：2010-09-23
申请人： Sun-il Kim , Young-soo Park , Jae-chul Park
发明人： Sun-il Kim , Young-soo Park , Jae-chul Park
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7869 , H01L29/78696
摘要： A transistor may include: a gate insulting layer, a gate electrode formed on a bottom side of the gate insulating layer, a channel layer formed on a top side of the gate insulating layer, a source electrode that contacts a first portion of the channel layer, and a drain electrode that contacts a second portion of the channel layer. The channel layer may have a double-layer structure, including an upper layer and a lower layer. The upper layer may have a carrier concentration lower than that of the lower layer. The upper layer may be doped with a carrier acceptor in order to have an electrical resistance higher than that of the lower layer.
摘要翻译：晶体管可以包括：栅极绝缘层，形成在栅极绝缘层的底侧的栅电极，形成在栅极绝缘层的顶侧的沟道层，源极与沟道层的第一部分接触以及与沟道层的第二部分接触的漏电极。沟道层可以具有双层结构，包括上层和下层。上层可以具有低于下层的载流子浓度。上层可以掺杂载体受体以使电阻高于下层的电阻。

69. 发明授权

US08222663B2 Light emitting device and method of manufacturing the same 有权
标题翻译：发光元件及其制造方法
公开(公告)号：US08222663B2
公开(公告)日：2012-07-17
申请号：US12458797
申请日：2009-07-23
申请人： Kyoung-kook Kim , Su-hee Chae , Young-soo Park , Taek Kim , Moon-seung Yang , Hyung-su Jeong , Jae-chul Park , Jun-youn Kim
发明人： Kyoung-kook Kim , Su-hee Chae , Young-soo Park , Taek Kim , Moon-seung Yang , Hyung-su Jeong , Jae-chul Park , Jun-youn Kim
IPC分类号： H01L33/00
CPC分类号： H01L33/0079 , H01L33/12
摘要： Provided is a light emitting diode (LED) manufactured by using a wafer bonding method and a method of manufacturing a LED by using a wafer bonding method. The wafer bonding method may include interposing a stress relaxation layer formed of a metal between a semiconductor layer and a bonding substrate. When the stress relaxation layer is used, stress between the bonding substrate and a growth substrate may be offset due to the flexibility of metal, and accordingly, bending or warpage of the bonding substrate may be reduced or prevented.
摘要翻译：提供了通过使用晶片接合方法制造的发光二极管（LED）和通过使用晶片接合方法制造LED的方法。晶片接合方法可以包括在半导体层和接合基板之间插入由金属形成的应力松弛层。当使用应力松弛层时，由于金属的柔韧性，接合基板和生长基板之间的应力可能被抵消，因此可以减少或防止接合基板的弯曲或翘曲。

70. 发明授权

US08143678B2 Thin film transistors having multi-layer channel 有权
标题翻译：具有多层通道的薄膜晶体管
公开(公告)号：US08143678B2
公开(公告)日：2012-03-27
申请号：US11987499
申请日：2007-11-30
申请人： Sun-il Kim , Young-soo Park , Jae-chul Park
发明人： Sun-il Kim , Young-soo Park , Jae-chul Park
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7869 , H01L29/78696
摘要： A transistor may include: a gate insulting layer; a gate electrode formed on the gate insulating layer; a channel layer formed on the gate insulating layer; and source and drain electrodes that contact the channel layer. The channel layer may have a double-layer structure, including upper and lower layers. The upper layer may have a carrier concentration lower than the lower layer. A method of manufacturing a transistor may include: forming a channel layer on a substrate; forming source and drain electrodes on the substrate; forming a gate insulating layer on the substrate; and forming a gate electrode on the gate insulating layer above the channel layer. A method of manufacturing a transistor may include: forming a gate electrode on a substrate; forming a gate insulating layer on the substrate; forming a channel layer on the gate insulating layer; and forming source and drain electrodes on the gate insulating layer.
摘要翻译：晶体管可以包括：栅极绝缘层; 形成在所述栅极绝缘层上的栅电极; 形成在所述栅极绝缘层上的沟道层; 以及与沟道层接触的源极和漏极。沟道层可以具有双层结构，包括上层和下层。上层可以具有低于下层的载流子浓度。制造晶体管的方法可以包括：在衬底上形成沟道层; 在基板上形成源极和漏极; 在所述基板上形成栅极绝缘层; 以及在沟道层上方的栅极绝缘层上形成栅电极。制造晶体管的方法可以包括：在衬底上形成栅电极; 在所述基板上形成栅极绝缘层; 在所述栅极绝缘层上形成沟道层; 以及在栅极绝缘层上形成源极和漏极。

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