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61. 发明申请

US20160283378A1 STORE OPERATIONS TO MAINTAIN CACHE COHERENCE 有权
公开(公告)号：US20160283378A1
公开(公告)日：2016-09-29
申请号：US14744055
申请日：2015-06-19
申请人： International Business Machines Corporation
发明人： Constantinos Evangelinos , Ravi Nair , Martin Ohmacht
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F8/4441 , G06F12/0837 , G06F12/0842 , G06F12/0875 , G06F2212/1024 , G06F2212/452 , G06F2212/622
摘要： In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.

62. 发明授权

US09448798B1 Silent store detection and recording in memory storage 有权
标题翻译：在存储器中静音存储检测和记录
公开(公告)号：US09448798B1
公开(公告)日：2016-09-20
申请号：US15086974
申请日：2016-03-31
申请人： International Business Machines Corporation
发明人： Pradip Bose , Chen-Yong Cher , Ravi Nair
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3863 , G06F11/00 , G06F11/30
摘要： An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memory location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.
摘要翻译：一方面包括接收包括存储器地址和写数据的写请求。从存储器地址的存储器位置读取存储的数据。基于确定存储器位置未被修改，将存储的数据与写入数据进行比较。基于与写入数据匹配的存储数据，写入请求完成，而不将写入数据写入存储器，并且在静默存储位图中设置相应的静默存储位。基于与写入数据不匹配的存储数据，将写入数据写入存储器位置，无声存储位被复位并且相应的修改位被置位。为应用程序和操作系统中的至少一个提供对静默存储位图的访问。

63. 发明授权

US09405711B2 On-chip traffic prioritization in memory 有权
标题翻译：内存中的片上流量优先级
公开(公告)号：US09405711B2
公开(公告)日：2016-08-02
申请号：US13737339
申请日：2013-01-09
申请人： International Business Machines Corporation
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F12/00 , G06F13/18 , G06F9/48 , G06F13/16
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0625 , G06F3/0673 , G06F9/4881 , G06F13/1626 , G06F13/1663 , G06F13/18 , Y02D10/14
摘要： According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.
摘要翻译：根据一个实施例，一种用于存储器设备中的业务优先级排序的方法包括：将存储器设备中的处理元件中包含优先级值的存储器访问请求发送到存储器设备中的交叉连接。存储器访问请求通过交叉开关互连路由到与存储器访问请求相关联的存储器设备中的存储器控制器。存储器访问请求在存储器控制器处被接收。将存储器访问请求的优先级值与存储在存储器控制器的队列中的多个存储器访问请求的优先级值进行比较，以确定最高优先级的存储器访问请求。存储器控制器基于最高优先级的存储器访问请求来执行下一个存储器访问请求。

64. 发明授权

US09400656B2 Chaining between exposed vector pipelines 有权
标题翻译：暴露的矢量管道之间的链接
公开(公告)号：US09400656B2
公开(公告)日：2016-07-26
申请号：US13966408
申请日：2013-08-14
申请人： International Business Machines Corporation
发明人： Thomas W. Fox , Bruce M. Fleischer , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3867 , G06F9/30079 , G06F9/3017 , G06F9/30185 , G06F9/3826 , G06F9/3828
摘要： Embodiments include a method for chaining data in an exposed-pipeline processing element. The method includes separating a multiple instruction word into a first sub-instruction and a second sub-instruction, receiving the first sub-instruction and the second sub-instruction in the exposed-pipeline processing element. The method also includes issuing the first sub-instruction at a first time, issuing the second sub-instruction at a second time different than the first time, the second time being offset to account for a dependency of the second sub-instruction on a first result from the first sub-instruction, the first pipeline performing the first sub-instruction at a first clock cycle and communicating the first result from performing the first sub-instruction to a chaining bus coupled to the first pipeline and a second pipeline, the communicating at a second clock cycle subsequent to the first clock cycle that corresponds to a total number of latch pipeline stages in the first pipeline.
摘要翻译：实施例包括用于在暴露流水线处理元件中链接数据的方法。该方法包括将多个指令字分离成第一子指令和第二子指令，在暴露流水线处理元件中接收第一子指令和第二子指令。该方法还包括在第一时间发出第一子指令，在与第一时间不同的第二时间发出第二子指令，第二时间被补偿以考虑第二子指令对第一子指令的依赖性来自第一子指令的结果是，第一流水线以第一时钟周期执行第一子指令，并将第一结果从执行第一子指令传送到耦合到第一流水线的链接总线和第二流水线，在第一时钟周期之后的第二时钟周期中，其对应于第一管线中的锁存流水线级的总数。

65. 发明授权

US09390038B2 Local bypass for in memory computing 有权
标题翻译：用于内存计算的本地旁路
公开(公告)号：US09390038B2
公开(公告)日：2016-07-12
申请号：US13966441
申请日：2013-08-14
申请人： International Business Machines Corporation
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair , Martin Ohmacht , Krishnan Sugavanam
IPC分类号： G06F13/28 , H01L25/18 , G06F21/72 , G06F13/364 , G06F9/38
CPC分类号： G06F13/364 , G06F9/3826 , G06F13/28 , G06F21/72 , H01L25/18 , H01L2924/0002 , H04L2209/125 , Y02D10/14 , H01L2924/00
摘要： Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network.
摘要翻译：实施例包括用于旁路有源存储器件中的数据的方法。该方法包括：请求者确定尚未传送给设保者的授权人的传送次数，根据满足阈值的传送次数，向互连网请求旁路路径用于传送，并通过基于请求的设保人的旁路路径，互连网络根据请求授予设保人的控制权。该方法还包括互连网络，其基于事件请求对设保人的控制，并且经由互连网络从其他请求者传送延迟的传输，延迟的传送由于授权者先前由请求者控制而延迟，基于控制进行通信的设保人被改回互连网络。

66. 发明授权

US09274971B2 Low latency data exchange 有权
公开(公告)号：US09274971B2
公开(公告)日：2016-03-01
申请号：US13685816
申请日：2012-11-27
申请人： International Business Machines Corporation
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans m. Jacobson , Ravi Nair
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , Y02D10/13
摘要： According to one embodiment, a method for exchanging data in a system that includes a main processor in communication with an active memory device is provided. The method includes a processing element in the active memory device receiving an instruction from the main processor and receiving a store request from a thread running on the main processor, the store request specifying a memory address associated with the processing element. The method also includes storing a value provided in the store request in a queue in the processing element and the processing element performing the instruction using the value from the queue.

67. 发明授权

US09268704B2 Low latency data exchange 有权
标题翻译：低延迟数据交换
公开(公告)号：US09268704B2
公开(公告)日：2016-02-23
申请号：US13787057
申请日：2013-03-06
申请人： International Business Machines Corporation
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , Y02D10/13
摘要： According to one embodiment, a method for exchanging data in a system that includes a main processor in communication with an active memory device is provided. The method includes a processing element in the active memory device receiving an instruction from the main processor and receiving a store request from a thread running on the main processor, the store request specifying a memory address associated with the processing element. The method also includes storing a value provided in the store request in a queue in the processing element and the processing element performing the instruction using the value from the queue.
摘要翻译：根据一个实施例，提供了一种用于在包括与主动存储器设备通信的主处理器的系统中交换数据的方法。该方法包括主动存储器装置中的处理元件，从主处理器接收指令，并从主处理器上运行的线程接收存储请求，存储请求指定与处理元件相关联的存储器地址。该方法还包括将存储请求中提供的值存储在处理元件中的队列中，并且处理元件使用来自队列的值来执行指令。

68. 发明授权

US09251048B2 Memory page management 有权
标题翻译：内存页面管理
公开(公告)号：US09251048B2
公开(公告)日：2016-02-02
申请号：US13655505
申请日：2012-10-19
申请人： International Business Machines Corporation
发明人： Bruce M. Fleischer , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0215 , G06F1/3275 , G06F12/08 , Y02D10/13 , Y02D10/14
摘要： According to one embodiment, a method for operating a memory device includes receiving a first request from a requestor, wherein the first request includes accessing data at a first memory location in a memory bank, opening a first page in the memory bank, wherein opening the first page includes loading a row including the first memory location into a buffer, the row being loaded from a row location in the memory bank and transmitting the data from the first memory location to the requestor. The method also includes determining, by a memory controller, whether to close the first page following execution of the first request based on information relating to a likelihood that a subsequent request will access the first page.
摘要翻译：根据一个实施例，一种用于操作存储设备的方法包括从请求者接收第一请求，其中第一请求包括在存储体中的第一存储器位置访问数据，打开存储体中的第一页，其中打开第一页包括将包括第一存储器位置的行加载到缓冲器中，该行从存储体中的行位置加载并将数据从第一存储器位置传送到请求器。该方法还包括由存储器控制器基于与随后的请求将访问第一页的可能性有关的信息确定第一请求执行之后是否关闭第一页。

69. 发明授权

US09110778B2 Address generation in an active memory device 有权
标题翻译：活动存储设备中的地址生成
公开(公告)号：US09110778B2
公开(公告)日：2015-08-18
申请号：US13671679
申请日：2012-11-08
申请人： International Business Machines Corporation
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F12/10 , G06F12/02
CPC分类号： G06F12/02 , G06F12/06 , G06F12/10 , Y02D10/13
摘要： Embodiments relate to address generation in an active memory device that includes memory and a processing element. An aspect includes a method for address generation in the active memory device. The method includes reading a base address value and an offset address value from a register file group of the processing element. The processing element determines a virtual address based on the base address value and the offset address value. The processing element translates the virtual address into a physical address and accesses a location in the memory based on the physical address.
摘要翻译：实施例涉及包括存储器和处理元件的有源存储器件中的地址生成。一方面包括在活动存储设备中产生地址的方法。该方法包括从处理元件的寄存器文件组读取基地址值和偏移地址值。处理元件根据基地址值和偏移地址值确定虚拟地址。处理元件将虚拟地址转换为物理地址，并基于物理地址访问存储器中的位置。

70. 发明申请

US20140281629A1 POWER MANAGEMENT FOR A COMPUTER SYSTEM 有权
公开(公告)号：US20140281629A1
公开(公告)日：2014-09-18
申请号：US13966414
申请日：2013-08-14
申请人： International Business Machines Corporation
发明人： Pradip Bose , Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , G06F1/3228 , G06F1/3234 , G06F1/3275 , G06F1/3278 , G06F3/0656 , G06F9/3877 , G06F9/44 , G06F9/4893 , G06F13/00 , G06F13/1663 , G06F2212/312 , Y02D10/152 , Y02D10/24 , Y02D50/20
摘要： Embodiments include a method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered units including a processing element. The method includes the main processor executing a program on a program thread, encountering a first section of code to be executed by the active memory device, changing, by a first command, a power state of a powered unit on the active memory device based on the main processor encountering the first section of code, the first command including a store command. The method also includes the processing element executing the first section of code at a second time, changing a power state of the main processor from a power use state to a power saving state based on the processing element executing the first section.

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