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61. 发明申请

US20180308207A1 COMPUTE OPTIMIZATION MECHANISM 审中-公开
公开(公告)号：US20180308207A1
公开(公告)日：2018-10-25
申请号：US15798574
申请日：2017-10-31
申请人： Intel Corporation
发明人： Abhishek R. Appu , Altug Koker , Linda L. Hurd , Dukhwan Kim , Mike B. Macpherson , John C. Weast , Feng Chen , Farshad Akhbari , Narayan Srinivasa , Nadathur Rajagopalan Satish , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Anbang Yao , Tatiana Shpeisman
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , G06F9/3001 , G06F9/3017 , G06F9/3851 , G06F9/3887 , G06F9/3895 , G06F9/46 , G06N3/063 , G06T15/005 , G06T15/04 , G09G5/363
摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit depth of floating point thread operations.

62. 发明申请

US20180307984A1 DYNAMIC DISTRIBUTED TRAINING OF MACHINE LEARNING MODELS 审中-公开
公开(公告)号：US20180307984A1
公开(公告)日：2018-10-25
申请号：US15494971
申请日：2017-04-24
申请人： Intel Corporation
发明人： Altug Koker , Abhishek R. Appu , Kamal Sinha , Joydeep Ray , Balaji Vembu , Elmoustapha Ould-Ahmed-Vall , Sara S. Baghsorkhi , Anbang Yao , Kevin Nealis , Xiaoming Chen , John C. Weast , Justin E. Gottschlich , Prasoonkumar Surti , Chandrasekaran Sakthivel , Farshad Akhbari , Nadathur Rajagopalan Satish , Liwei Ma , Jeremy Bottleson , Eriko Nurvitadhi , Travis T. Schluessler , Ankur N. Shah , Jonathan Kennedy , Vasanth Ranganathan , Sanjeev Jahagirdar
IPC分类号： G06N3/08 , G06N99/00
CPC分类号： G06N3/08 , G06F9/28 , G06F9/505 , G06N3/0445 , G06N3/0454 , G06N3/0481 , G06N3/063 , G06N99/005
摘要： In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

63. 发明申请

US20170185403A1 Hardware content-associative data structure for acceleration of set operations 审中-公开
公开(公告)号：US20170185403A1
公开(公告)日：2017-06-29
申请号：US14757776
申请日：2015-12-23
申请人： Intel Corporation
发明人： Michael J. Anderson , Sheng R. Li , Jong Soo Park , Md Mostofa Ali Patwary , Nadathur Rajagopalan Satish , Mikhail Smelyanskiy , Narayanan Sundaram
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F9/3016 , G06F9/30018 , G06F9/30021 , G06F9/3005 , G06F9/3877 , G06F12/0875 , G06F16/9014 , G06F17/10 , G06F2212/452
摘要： A processor includes a front end to receive an instruction, a decoder to decode the instruction, a set operations logic unit (SOLU) to execute the instruction, and a retirement unit to retire the instruction. The SOLU includes logic to store a first set of key-value pairs in a content-associative data structure, to receive a second set of key-value pairs, and to identify key-value pairs in the two sets with matching keys. The SOLU includes logic to add the second set of key-value pairs to the first set to produce an output set, and to apply an operation to the values of key-value pairs with matching keys, generating a single value for the matching key. The SOLU includes logic to produce an output set that includes key-value pairs from the first set with matching keys, and to discard key-value pairs from the first set with unique keys.

64. 发明申请

US20170168827A1 SORTING DATA AND MERGING SORTED DATA IN AN INSTRUCTION SET ARCHITECTURE 审中-公开
公开(公告)号：US20170168827A1
公开(公告)日：2017-06-15
申请号：US14969864
申请日：2015-12-15
申请人： Intel Corporation
发明人： Asit K. Mishra , Deborah T. Marr , Jong Soo Park , Nadathur Rajagopalan Satish , Mikhail Smelyanskiy , Michael Anderson , Mostofa Ali Patwary , Narayanan Sundaram , Sheng Li
IPC分类号： G06F9/30
CPC分类号： G06F9/30192 , G06F9/30021 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30145
摘要： A processing device includes a sorting module, which adds to each of a plurality of elements a position value of a corresponding position in a register rest resulting in a plurality of transformed elements in corresponding positions. The plurality of elements include a plurality of bits. The sorting module compares each of the plurality of transformed elements to itself and to one another. The sorting module also assigns one of an enabled or disabled indicator to each of the plurality of the transformed elements based on the comparison. The sorting module further counts a number of the enabled indicators assigned to each of the plurality of the transformed elements to generate a sorted sequence of the plurality of elements.

65. 发明授权

US09154157B2 Search unit to accelerate variable length compression/decompression 有权
标题翻译：搜索单元加速可变长度压缩/解压缩
公开(公告)号：US09154157B2
公开(公告)日：2015-10-06
申请号：US13629467
申请日：2012-09-27
申请人： Intel Corporation
发明人： Nadathur Rajagopalan Satish , Changkyu Kim , Jatin Chhugani
IPC分类号： G06F17/30 , H03M7/30
CPC分类号： H03M7/30
摘要： Systems and methods to accelerate compression and decompression with a search unit implemented in the processor core. According to an embodiment, a search unit may be implemented to perform compression or decompression on an input stream of data. The search unit may use a look-up table to identify appropriate compression or decompression symbols. The look-up table may be populated with a table derived using the variable length coding symbols of a sequence of vertices to be compressed or extracted from a received data stream to be decompressed. A comparator and a finite state machine may be implemented in the search unit to facilitate traversal of the look-up table.
摘要翻译：用处理器核心实现的搜索单元来加速压缩和解压缩的系统和方法。根据实施例，可以实现搜索单元以对输入的数据流执行压缩或解压缩。搜索单元可以使用查找表来标识适当的压缩或解压缩符号。查找表可以使用将要从要被解压缩的接收数据流压缩或提取的顶点序列的可变长度编码符号导出的表来填充。可以在搜索单元中实现比较器和有限状态机，以便于遍历查找表。

66. 发明授权

US12056788B2 Compute optimization mechanism 有权
公开(公告)号：US12056788B2
公开(公告)日：2024-08-06
申请号：US17684187
申请日：2022-03-01
申请人： Intel Corporation
发明人： Abhishek R. Appu , Altug Koker , Linda L. Hurd , Dukhwan Kim , Mike B. Macpherson , John C. Weast , Feng Chen , Farshad Akhbari , Narayan Srinivasa , Nadathur Rajagopalan Satish , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Anbang Yao , Tatiana Shpeisman
IPC分类号： G06T1/20 , G06F3/14 , G06F9/30 , G06F9/38 , G06N3/044 , G06N3/045 , G06N3/063 , G06N3/084 , G06T15/00 , G09G5/36 , G06T15/04
CPC分类号： G06T1/20 , G06F3/14 , G06F9/3001 , G06F9/30014 , G06F9/3017 , G06F9/3887 , G06F9/3895 , G06N3/044 , G06N3/045 , G06N3/063 , G06N3/084 , G06T15/005 , G09G5/363 , G06F9/3851 , G06T15/04 , G09G2360/06 , G09G2360/08 , G09G2360/121
摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core including mixed-precision execution circuitry to execute one or more of the mixed-precision instructions to perform a mixed-precision dot-product operation comprising to perform a set of multiply and accumulate operations.

67. 发明公开

US20240257294A1 COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS 审中-公开
公开(公告)号：US20240257294A1
公开(公告)日：2024-08-01
申请号：US18436494
申请日：2024-02-08
申请人： Intel Corporation
发明人： Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
IPC分类号： G06T1/20 , G06F8/41 , G06F9/455 , G06F9/50 , G06N3/044 , G06N3/045 , G06N3/063 , G06N3/084
CPC分类号： G06T1/20 , G06F9/45533 , G06F9/5061 , G06F9/5094 , G06N3/044 , G06N3/045 , G06N3/063 , G06N3/084 , G06F8/41 , G06F2009/45583
摘要： Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

68. 发明授权

US11922535B2 Compute optimization mechanism for deep neural networks 有权
公开(公告)号：US11922535B2
公开(公告)日：2024-03-05
申请号：US18168207
申请日：2023-02-13
申请人： Intel Corporation
发明人： Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
IPC分类号： G06T1/20 , G06F9/455 , G06F9/50 , G06N3/044 , G06N3/045 , G06N3/063 , G06N3/084 , G06F8/41
CPC分类号： G06T1/20 , G06F9/45533 , G06F9/5061 , G06F9/5094 , G06N3/044 , G06N3/045 , G06N3/063 , G06N3/084 , G06F8/41 , G06F2009/45583
摘要： Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

69. 发明公开

US20240004829A1 GRAPHICS PROCESSING INTEGRATED CIRCUIT PACKAGE 审中-公开
公开(公告)号：US20240004829A1
公开(公告)日：2024-01-04
申请号：US18350902
申请日：2023-07-12
申请人： Intel Corporation
发明人： Altug Koker , Farshad Akhbari , Feng Chen , Dukhwan Kim , Narayan Srinivasa , Nadathur Rajagopalan Satish , Liwei Ma , Jeremy Bottleson , Eriko Nurvitadhi , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Tatiana Shpeisman , Abhishek R. Appu
IPC分类号： G06F15/80 , G06F13/40 , G06T1/20 , G06F9/30 , G06F13/00 , G06N3/063 , G06N3/084 , G06N3/044 , G06N3/045 , G06N3/048
CPC分类号： G06F15/8007 , G06F13/4027 , G06T1/20 , G06F9/3004 , G06F13/00 , G06N3/063 , G06N3/084 , G06N3/044 , G06N3/045 , G06N3/048
摘要： An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

70. 发明授权

US11797837B2 Dynamic distributed training of machine learning models 有权
公开(公告)号：US11797837B2
公开(公告)日：2023-10-24
申请号：US15494971
申请日：2017-04-24
申请人： Intel Corporation
发明人： Altug Koker , Abhishek R. Appu , Kamal Sinha , Joydeep Ray , Balaji Vembu , Elmoustapha Ould-Ahmed-Vall , Sara S. Baghsorkhi , Anbang Yao , Kevin Nealis , Xiaoming Chen , John C. Weast , Justin E. Gottschlich , Prasoonkumar Surti , Chandrasekaran Sakthivel , Farshad Akhbari , Nadathur Rajagopalan Satish , Liwei Ma , Jeremy Bottleson , Eriko Nurvitadhi , Travis T. Schluessler , Ankur N. Shah , Jonathan Kennedy , Vasanth Ranganathan , Sanjeev Jahagirdar
IPC分类号： G06N3/08 , G06N20/00 , G06N3/063 , G06N3/044 , G06N3/045 , G06N3/048
CPC分类号： G06N3/08 , G06N3/044 , G06N3/045 , G06N3/063 , G06N20/00 , G06N3/048
摘要： In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

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