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61. 发明授权

US08835316B2 Transistor with primary and semiconductor spacer, method for manufacturing transistor, and semiconductor chip comprising the transistor 有权
标题翻译：具有初级和半导体衬垫的晶体管，晶体管的制造方法和包括晶体管的半导体芯片
公开(公告)号：US08835316B2
公开(公告)日：2014-09-16
申请号：US13378997
申请日：2011-08-09
申请人： Haizhou Yin , Jun Luo , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Jun Luo , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/772 , H01L21/3213 , H01L21/768 , H01L29/78 , H01L29/66 , H01L29/417 , H01L21/285
CPC分类号： H01L29/7833 , H01L21/28518 , H01L21/32139 , H01L21/76897 , H01L29/41775 , H01L29/665 , H01L29/6659
摘要： The disclosure provides a transistor, a method for manufacturing the transistor, and a semiconductor chip comprising the transistor. The transistor comprises: an active area, a gate stack, a primary spacer, and source/drain regions, wherein the active area is on a semiconductor substrate; the gate stack, the primary spacer, and the source/drain regions are on the active area; the primary spacer surrounds the gate stack; the source/drain regions are embedded in the active area and self-aligned with opposite sides of the primary spacer. Wherein the transistor further comprises: a silicide spacer, wherein the silicide spacer is located at opposite sides of the primary spacer, and a dielectric material is filled between the two ends of the silicide spacer in the width direction of the gate stack, so as to isolate the source/drain regions from each other.
摘要翻译：本发明提供一种晶体管，一种晶体管的制造方法和一种包括该晶体管的半导体芯片。晶体管包括：有源区，栅极堆叠，初级间隔物和源/漏区，其中有源区在半导体衬底上; 栅极堆叠，初级间隔物和源极/漏极区域在有源区域上; 主要间隔物围绕栅极堆叠; 源极/漏极区域被嵌入有源区域中并且与主隔板的相对侧自对准。其中，所述晶体管还包括：硅化物间隔物，其中所述硅化物间隔物位于所述主间隔物的相对侧，并且电介质材料填充在所述硅化物间隔物的所述栅堆叠的宽度方向的两端之间，以便将源极/漏极区彼此隔离。

62. 发明授权

US08829621B2 Semiconductor substrate for manufacturing transistors having back-gates thereon 有权
标题翻译：用于制造其上具有背栅的晶体管的半导体衬底
公开(公告)号：US08829621B2
公开(公告)日：2014-09-09
申请号：US13696995
申请日：2011-11-29
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin , Huicai Zhong
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin , Huicai Zhong
IPC分类号： H01L21/70 , H01L27/12 , H01L21/84 , H01L27/092 , H01L21/74 , H01L21/762 , H01L29/786
CPC分类号： H01L27/12 , H01L21/743 , H01L21/762 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/78648 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a semiconductor substrate, an integrated circuit having the semiconductor substrate, and methods of manufacturing the same. The semiconductor substrate for use in an integrated circuit comprising transistors having back-gates according to the present invention comprises: a semiconductor base layer; a first insulating material layer on the semiconductor base layer; a first conductive material layer on the first insulating material layer; a second insulating material layer on the first conductive material layer; a second conductive material layer on the second insulating material layer; an insulating buried layer on the second conductive material layer; and a semiconductor layer on the insulating buried layer, wherein at least one first conductive via is provided between the first conductive material layer and the second conductive material layer to penetrate through the second insulating material layer so as to connect the first conductive material layer with the second conductive material layer, the position of each of the first conductive vias being defined by a region in which a corresponding one of a first group of transistors is to be formed.
摘要翻译：本发明涉及半导体衬底，具有半导体衬底的集成电路及其制造方法。根据本发明的包括具有背栅的晶体管的集成电路中使用的半导体衬底包括：半导体基底层; 半导体基底层上的第一绝缘材料层; 第一绝缘材料层上的第一导电材料层; 在所述第一导电材料层上的第二绝缘材料层; 在所述第二绝缘材料层上的第二导电材料层; 第二导电材料层上的绝缘掩埋层; 以及在所述绝缘埋层上的半导体层，其中，在所述第一导电材料层和所述第二导电材料层之间设置有至少一个第一导电通孔，以穿透所述第二绝缘材料层，以将所述第一导电材料层与第二导电材料层，每个第一导电通孔的位置由要形成第一组晶体管中的对应一个的区域限定。

63. 发明授权

US08815660B2 Structure and method for reducing floating body effect of SOI MOSFETs 有权
标题翻译：减少SOI MOSFET浮体效应的结构和方法
公开(公告)号：US08815660B2
公开(公告)日：2014-08-26
申请号：US12700797
申请日：2010-02-05
申请人： Qingqing Liang , Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Qingqing Liang , Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/786
CPC分类号： H01L27/1203 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L29/6675 , H01L29/78615 , H01L29/78624 , H01L29/78687
摘要： The present invention generally relates to a semiconductor structure and method, and more specifically, to a structure and method for reducing floating body effect of silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). An integrated circuit (IC) structure includes a SOI substrate and at least one MOSFET formed on the SOI substrate. Additionally, the IC structure includes an asymmetrical source-drain junction in the at least one MOSFET by damaging a pn junction to reduce floating body effects of the at least one MOSFET.
摘要翻译：本发明一般涉及半导体结构和方法，更具体地说，涉及用于减少绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）的浮体效应的结构和方法。集成电路（IC）结构包括SOI衬底和形成在SOI衬底上的至少一个MOSFET。此外，IC结构包括通过损坏pn结在至少一个MOSFET中的不对称源极 - 漏极结，以减少至少一个MOSFET的浮体效应。

64. 发明授权

US08729611B2 Semiconductor device having a plurality of fins with different heights and method for manufacturing the same 有权
标题翻译：具有多个具有不同高度的翅片的半导体器件及其制造方法
公开(公告)号：US08729611B2
公开(公告)日：2014-05-20
申请号：US13503693
申请日：2011-11-18
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/088
CPC分类号： H01L21/845 , H01L27/1211
摘要： The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor layer comprising a plurality of semiconductor sub-layers; and a plurality of fins formed in the semiconductor layer and adjoining the semiconductor layer, wherein at least two of the plurality of fins comprise different numbers of the semiconductor sub-layers and have different heights. According to the present disclosure, a plurality of semiconductor devices with different dimensions and different driving abilities can be integrated on a single wafer.
摘要翻译：本发明提供一种半导体器件及其制造方法。半导体器件包括：包括多个半导体子层的半导体层; 以及形成在所述半导体层中并与所述半导体层相邻的多个鳍，其中所述多个鳍中的至少两个鳍包括不同数量的半导体子层并具有不同的高度。根据本公开，可以在单个晶片上集成具有不同尺寸和不同驱动能力的多个半导体器件。

65. 发明授权

US08692335B2 Source/drain region, contact hole and method for forming the same 有权
标题翻译：源/漏区，接触孔及其形成方法
公开(公告)号：US08692335B2
公开(公告)日：2014-04-08
申请号：US13119074
申请日：2011-02-18
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/02
CPC分类号： H01L29/0847 , H01L21/76805 , H01L21/823807 , H01L21/823814 , H01L29/66636 , H01L29/78
摘要： An S/D region including a first region and a second region is provided. The first region is located, with at least a partial thickness, in the substrate. The second region is formed on the first region and made of a material different from that of the first region. A method for forming an S/D region is further provided, and the method includes: forming trenches at both sides of a gate stack structure in a substrate; forming a first semiconductor layer, wherein at least a part of the first semiconductor layer is filled into the trenches; and forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer is made of a material different from that of the first semiconductor layer. A contact hole and a forming method thereof are also provided which may increase the contact area between a contact hole and a contact region, and reduce the contact resistance.
摘要翻译：提供包括第一区域和第二区域的S / D区域。第一区域在衬底中具有至少部分厚度。第二区域形成在第一区域上并且由与第一区域不同的材料制成。还提供了形成S / D区域的方法，该方法包括：在基板中的栅叠层结构的两侧形成沟槽; 形成第一半导体层，其中所述第一半导体层的至少一部分被填充到所述沟槽中; 以及在所述第一半导体层上形成第二半导体层，其中所述第二半导体层由与所述第一半导体层不同的材料制成。还提供接触孔及其形成方法，其可以增加接触孔和接触区域之间的接触面积，并降低接触电阻。

66. 发明授权

US08669155B2 Hybrid channel semiconductor device and method for forming the same 有权
标题翻译：混合通道半导体器件及其形成方法
公开(公告)号：US08669155B2
公开(公告)日：2014-03-11
申请号：US13142790
申请日：2011-04-11
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/8258
摘要： A hybrid channel semiconductor device and a method for forming the same are provided. The method includes: providing a first semiconductor layer, the first semiconductor layer including an NMOS area and a PMOS area, a surface of the first semiconductor layer being covered by a second semiconductor layer, wherein electrons have higher mobility than holes in one of the first semiconductor layer and the second semiconductor layer, and holes have higher mobility than electrons in the other; forming a first dummy gate structure, and a first source region and a first drain region on respective sides of the first dummy gate structure on the second semiconductor layer in the NMOS area, forming a second dummy gate structure, and a second source region and a second drain region on respective sides of the second dummy gate structure on the second semiconductor layer in the PMOS area; forming an interlayer dielectric layer on the second semiconductor layer and performing planarization; removing the first dummy gate structure and the second dummy gate structure to form a first opening and a second opening; and forming a first gate structure on the one of the first semiconductor layer and the second semiconductor layer in which electrons have higher mobility in the first opening, and forming a second gate structure on the other semiconductor layer in the second opening. The invention can reduce defects in the channel region.
摘要翻译：提供混合通道半导体器件及其形成方法。该方法包括：提供第一半导体层，第一半导体层包括NMOS区域和PMOS区域，第一半导体层的表面被第二半导体层覆盖，其中电子具有比第一半导体层半导体层和第二半导体层，并且空穴在另一个中具有比电子更高的迁移率; 在所述NMOS区域中的所述第二半导体层上形成第一虚拟栅极结构以及所述第一虚拟栅极结构的相应侧上的第一源极区域和第一漏极区域，形成第二虚拟栅极结构，以及第二源极区域和在PMOS区域中的第二半导体层上的第二伪栅极结构的各个侧面上的第二漏极区域; 在所述第二半导体层上形成层间电介质层并进行平坦化; 去除第一虚拟栅极结构和第二虚拟栅极结构以形成第一开口和第二开口; 以及在所述第一半导体层和所述第二半导体层中的所述第一开口中形成具有较高迁移率的第一栅极结构，以及在所述第二开口中的另一半导体层上形成第二栅极结构。本发明可以减少通道区域的缺陷。

67. 发明授权

US08664091B2 Method for removing metallic nanotube 有权
标题翻译：去除金属纳米管的方法
公开(公告)号：US08664091B2
公开(公告)日：2014-03-04
申请号：US13504043
申请日：2011-11-21
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/479
CPC分类号： B82Y40/00 , B82B3/0076
摘要： A method for removing a metallic nanotube, which is formed on a substrate in a first direction, includes forming a plurality of conductors in a second direction crossing the first direction, electrically contacting the plurality of conductors with metallic nanotube, respectively, forming at least two voltage-applying electrodes on the conductors, each of which electrically contacting at least one of the conductors, and applying voltages to at least some of the conductors through the voltage-applying electrodes, respectively. Among the conductors to which the voltages are respectively applied, every two adjacent conductors have an electrical potential difference created therebetween, so as to burn out the metallic nanotube.
摘要翻译：一种在第一方向上形成在基板上的金属纳米管的除去方法包括在与第一方向交叉的第二方向上形成多个导体，分别与多个导体与金属纳米管电接触，形成至少两个导体上的施加电压的电极分别与至少一个导体电接触，并且通过电压施加电极分别向至少一些导体施加电压。在分别施加电压的导体中，每两个相邻的导体之间产生电位差，从而烧毁金属纳米管。

68. 发明授权

US08658485B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08658485B2
公开(公告)日：2014-02-25
申请号：US12937321
申请日：2010-06-28
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/823835 , H01L21/823814 , H01L21/823871 , H01L29/4966 , H01L29/665 , H01L29/66545 , H01L29/6656
摘要： There is provided a semiconductor device and a method of fabricating the same. The method of fabricating a semiconductor device according to the present invention comprises: forming a transistor structure including a gate, and source and drain regions on a semiconductor substrate; carrying out a first silicidation to form a first metal silicide layer on the source and drain regions; depositing a first dielectric layer on the substrate, the top of the first dielectric layer being flush with the top of the gate region; forming contact holes at the portions corresponding to the source and drain regions in the first dielectric layer; and carrying out a second silicidation to form a second metal silicide at the gate region and in the contact holes, wherein the first metal silicide layer is formed to prevent silicidation from occurring at the source and drain regions during the second silicidation.
摘要翻译：提供了一种半导体器件及其制造方法。根据本发明的制造半导体器件的方法包括：在半导体衬底上形成包括栅极和源极和漏极区域的晶体管结构; 进行第一硅化，以在源区和漏区上形成第一金属硅化物层; 在所述衬底上沉积第一介电层，所述第一介电层的顶部与所述栅极区的顶部齐平; 在与第一电介质层中的源极和漏极区对应的部分处形成接触孔; 并且在所述栅极区和所述接触孔中进行第二硅化以形成第二金属硅化物，其中形成所述第一金属硅化物层以防止在所述第二硅化期间在所述源极和漏极区发生硅化。

69. 发明授权

US08633522B2 Semiconductor structure and method for fabricating the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08633522B2
公开(公告)日：2014-01-21
申请号：US13062733
申请日：2010-09-20
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Huicai Zhong
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Huicai Zhong
IPC分类号： H01L29/78
CPC分类号： H01L29/7834 , H01L21/76224 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： A semiconductor structure and a method for fabricating the same. A semiconductor structure includes a semiconductor substrate; a channel region formed in the semiconductor substrate; a gate including a dielectric layer and a conductive layer and formed above the channel region; source and drain regions formed at opposing sides of the gate; first shallow trench isolations embedded into the semiconductor substrate and having a length direction parallel to the length direction of the gate; and second shallow trench isolations, each of which abuts the outer sidewall of the source or the drain region and abuts the first shallow trench isolations, in which the source and drain regions include first seed crystal layers abutting the second shallow trench isolations, and the top surfaces of the second shallow trench isolations are higher than or as high as the top surfaces of the source and drain regions.
摘要翻译：半导体结构及其制造方法。半导体结构包括半导体衬底; 形成在所述半导体衬底中的沟道区; 包括电介质层和导电层并形成在沟道区上方的栅极; 源极和漏极区域形成在栅极的相对侧; 第一浅沟槽隔离物嵌入半导体衬底并具有平行于栅极长度方向的长度方向; 以及第二浅沟槽隔离件，每个隔离件邻接源极或漏极区域的外侧壁并邻接第一浅沟槽隔离物，其中源极和漏极区域包括邻接第二浅沟槽隔离物的第一晶种层和顶部第二浅沟槽隔离物的表面高于或高于源区和漏区的顶表面。

70. 发明授权

US08575654B2 Method of forming strained semiconductor channel and semiconductor device 有权
标题翻译：形成应变半导体通道和半导体器件的方法
公开(公告)号：US08575654B2
公开(公告)日：2013-11-05
申请号：US13059285
申请日：2010-09-19
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/66651 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L29/1054 , H01L29/517 , H01L29/66545
摘要： A method of forming a strained semiconductor channel, comprising: forming a relaxed SiGe layer on a semiconductor substrate; forming a dielectric layer on the relaxed SiGe layer and forming a sacrificial gate on the dielectric layer, wherein the dielectric layer and the sacrificial gate form a sacrificial gate structure; depositing an interlayer dielectric layer, which is planarized to expose the sacrificial gate; etching to remove the sacrificial gate and the dielectric layer to form an opening; forming a semiconductor epitaxial layer by selective semiconductor epitaxial growth in the opening; depositing a high-K dielectric layer and a metal layer; and removing the high-K dielectric layer and metal layer covering the interlayer dielectric layer by planarizing the deposited metal layer and high-K dielectric layer to form a metal gate. A semiconductor device manufactured by this process is also provided.
摘要翻译：一种形成应变半导体沟道的方法，包括：在半导体衬底上形成弛豫的SiGe层; 在弛豫的SiGe层上形成电介质层，并在电介质层上形成牺牲栅极，其中电介质层和牺牲栅极形成牺牲栅极结构; 沉积层间电介质层，其被平坦化以暴露所述牺牲栅极; 蚀刻去除牺牲栅极和电介质层以形成开口; 通过开口中的选择性半导体外延生长形成半导体外延层; 沉积高K电介质层和金属层; 并且通过平坦化沉积的金属层和高K电介质层来去除覆盖层间电介质层的高K电介质层和金属层，以形成金属栅极。还提供了通过该方法制造的半导体器件。

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