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61. 发明申请

US20100133647A1 Semiconductor devices and semiconductor device manufacturing methods 审中-公开
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US20100133647A1
公开(公告)日：2010-06-03
申请号：US12591718
申请日：2009-11-30
申请人： Won-joo Kim , Sang-moo Choi , Tae-hee Lee , Yoon-dong Park
发明人： Won-joo Kim , Sang-moo Choi , Tae-hee Lee , Yoon-dong Park
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L27/1203 , H01L21/76224 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/1207 , H01L29/7841
摘要： Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a peripheral device than to a memory cell having the SOI structure.
摘要翻译：半导体器件和半导体器件制造方法。半导体器件制造方法可以通过使用选择性蚀刻在体半导体衬底的一个或多个局部区域中形成具有绝缘体上硅（SOI）结构的存储单元。因此，与具有SOI结构的存储单元相比，可以向外围设备施加不同的偏置电压。

62. 发明申请

US20100127759A1 Method of operating semiconductor device 有权
标题翻译：操作半导体器件的方法
公开(公告)号：US20100127759A1
公开(公告)日：2010-05-27
申请号：US12591202
申请日：2009-11-12
申请人： Sang-moo Choi , Won-joo Kim , Tae-hee Lee
发明人： Sang-moo Choi , Won-joo Kim , Tae-hee Lee
IPC分类号： H03K3/01
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/10844 , H01L29/7841 , H01L29/78654
摘要： Provided is a method of operating a semiconductor device, in which a gate voltage or a drain voltage is adjusted in order to add carriers to or remove carriers from a body region, thereby realizing semiconductor having a plurality of data states.
摘要翻译：提供了一种操作半导体器件的方法，其中调整栅极电压或漏极电压以便将载体添加到身体区域或从身体区域移除载体，从而实现具有多个数据状态的半导体。

63. 发明授权

US07679960B2 Non-volatile memory device and method of operating the same 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US07679960B2
公开(公告)日：2010-03-16
申请号：US11980358
申请日：2007-10-31
申请人： Jae-woong Hyun , Kyu-charn Park , Yoon-dong Park , Won-joo Kim , Young-gu Jin , Suk-pil Kim , Kyoung-Iae Cho , Jung-hoon Lee , Seung-hwan Song
发明人： Jae-woong Hyun , Kyu-charn Park , Yoon-dong Park , Won-joo Kim , Young-gu Jin , Suk-pil Kim , Kyoung-Iae Cho , Jung-hoon Lee , Seung-hwan Song
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L27/1203
摘要： A highly integrated non-volatile memory device and a method of operating the non-volatile memory device are provided. The non-volatile memory device includes a semiconductor layer. A plurality of upper control gate electrodes are arranged above the semiconductor layer. A plurality of lower control gate electrodes are arranged below the semiconductor layer, and the plurality of upper control gate electrodes and the plurality of lower control gate electrodes are disposed alternately. A plurality of upper charge storage layers are interposed between the semiconductor layer and the upper control gate electrodes. A plurality of lower charge storage layers are interposed between the semiconductor layer and the lower control gate electrodes.
摘要翻译：提供高度集成的非易失性存储器件和操作非易失性存储器件的方法。非易失性存储器件包括半导体层。多个上控制栅电极设置在半导体层的上方。多个下部控制栅电极配置在半导体层的下方，多个上部控制栅极电极和多个下部控制栅极电极交替配置。多个上电荷存储层插入在半导体层和上控制栅电极之间。多个下电荷存储层插入在半导体层和下控制栅电极之间。

64. 发明申请

US20100012186A1 Bulb-Type Light Concentrated Solar Cell Module 审中-公开
标题翻译：灯泡型集中太阳能电池模块
公开(公告)号：US20100012186A1
公开(公告)日：2010-01-21
申请号：US12436832
申请日：2009-05-07
申请人： Yoon-dong Park , Kwang-soo Seol , Deok-kee Kim , Won-joo Kim , Young-gu Jin , Seung-hoon Lee , Suk-pil Kim
发明人： Yoon-dong Park , Kwang-soo Seol , Deok-kee Kim , Won-joo Kim , Young-gu Jin , Seung-hoon Lee , Suk-pil Kim
IPC分类号： H01L31/00
CPC分类号： H01L35/32 , H01L31/0547 , H02S10/10 , Y02E10/52
摘要： Provided is a bulb-type light concentrated solar cell module that includes a reflective mirror unit that is concavely formed to convergingly reflect sunlight and has a first hole on a bottom thereof; a solar cell that generates electrical energy in response to light received from the reflective mirror unit; a socket that blocks the first hole at a lower part of the reflective mirror unit and is fixed on the reflective mirror unit; and a power control unit that is electrically connected to the solar cell to generate electricity in the socket.
摘要翻译：本发明提供一种灯泡型光集中太阳能电池模块，其包括反射镜单元，该反射镜单元凹入地形成以会聚地反射太阳光，并且在其底部具有第一孔; 太阳能电池，其响应于从所述反射镜单元接收的光产生电能; 插座，其阻挡反射镜单元的下部的第一孔并固定在反射镜单元上; 以及电连接到太阳能电池以在插座中发电的电力控制单元。

65. 发明授权

US07626685B2 Distance measuring sensors including vertical photogate and three-dimensional color image sensors including distance measuring sensors 有权
标题翻译：距离测量传感器包括垂直光栅和三维彩色图像传感器，包括距离测量传感器
公开(公告)号：US07626685B2
公开(公告)日：2009-12-01
申请号：US12222208
申请日：2008-08-05
申请人： Young-gu Jin , Yoon-dong Park , Won-joo Kim , Seung-hoon Lee , In-sung Joe
发明人： Young-gu Jin , Yoon-dong Park , Won-joo Kim , Seung-hoon Lee , In-sung Joe
IPC分类号： G01C3/08 , H01L31/062
CPC分类号： G01C3/08 , G01S7/4863 , G01S17/89
摘要： A distance measuring sensor may include: a photoelectric conversion region; first and second charge storage regions; first and second trenches; and/or first and second vertical photogates. The photoelectric conversion region may be in a substrate and/or may be doped with a first impurity in order to generate charges in response to received light. The first and second charge storage regions may be in the substrate and/or may be doped with a second impurity in order to collect charges. The first and second trenches may be formed to have depths in the substrate that correspond to the first and second charge storage regions, respectively. The first and second vertical photogates may be respectively in the first and second trenches. A three-dimensional color image sensor may include a plurality of unit pixels. Each unit pixel may include a plurality of color pixels and the distance measuring sensor.
摘要翻译：距离测量传感器可以包括：光电转换区域; 第一和第二电荷存储区域; 第一和第二壕沟; 和/或第一和第二垂直摄影门。光电转换区域可以在衬底中和/或可以掺杂第一杂质，以响应于接收的光产生电荷。第一和第二电荷存储区域可以在衬底中和/或可以掺杂第二杂质以便收集电荷。第一沟槽和第二沟槽可以形成为分别对应于第一和第二电荷存储区域的衬底中的深度。第一和第二垂直摄影门可以分别在第一和第二沟槽中。三维彩色图像传感器可以包括多个单位像素。每个单位像素可以包括多个彩色像素和距离测量传感器。

66. 发明授权

US07622765B2 Non-volatile memory device and a method of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07622765B2
公开(公告)日：2009-11-24
申请号：US11709057
申请日：2007-02-22
申请人： Won-joo Kim , Yoon-dong Park , Jung-hoon Lee
发明人： Won-joo Kim , Yoon-dong Park , Jung-hoon Lee
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11519 , H01L29/42332 , H01L29/792
摘要： A non-volatile memory device and a method of fabricating the same are provided. A non-volatile memory device may include a semiconductor substrate including a body and at least one pair of fins vertically protruding from the body and spaced apart from each other, and at least one control gate electrode on at least portions of outer side surfaces of the at least one pair of fins and extending onto top portions of the at least one pair of fins on an angle with the at least one pair of fins. The non-volatile memory device may further include at least one pair of gate insulating layers between the at least one control gate electrode and the at least one pair of fins, and at least one pair of storage node layers between the at least one pair of gate insulating layers and at least a portion of the at least one control gate electrode. The at least one control gate electrode may extend onto top portions of the at least one pair of fins in a zigzag fashion.
摘要翻译：提供了一种非易失性存储器件及其制造方法。非易失性存储器件可以包括半导体衬底，其包括主体和从主体垂直突出并且彼此间隔开的至少一对鳍，以及至少一个控制栅电极，其位于至少一个的外侧表面的至少部分上至少一对翅片，并且与所述至少一对翅片成角度地延伸到所述至少一对翅片的顶部上。非易失性存储器件还可以包括至少一对控制栅电极与至少一对散热片之间的至少一对栅绝缘层，以及至少一对控制栅电极之间的至少一对存储节点层栅绝缘层和至少一个控制栅电极的至少一部分。至少一个控制栅极可以以锯齿形的方式延伸到至少一对翅片的顶部。

67. 发明授权

US07535049B2 Multi bits flash memory device and method of operating the same 失效
标题翻译：多位闪存器件及其操作方法
公开(公告)号：US07535049B2
公开(公告)日：2009-05-19
申请号：US11249393
申请日：2005-10-14
申请人： Won-joo Kim , Yoon-dong Park , Eun-hong Lee , Sun-ae Seo , Sang-min Shin , Jung-hoon Lee , Seung-hyuk Chang
发明人： Won-joo Kim , Yoon-dong Park , Eun-hong Lee , Sun-ae Seo , Sang-min Shin , Jung-hoon Lee , Seung-hyuk Chang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： G11C11/5621 , B82Y10/00 , G11C11/5607 , G11C11/5628 , G11C11/5657 , G11C13/025 , H01L21/28273 , H01L21/28282 , H01L21/28291 , H01L29/0692 , H01L29/4232 , H01L29/7923
摘要： A multi bits flash memory device and a method of operating the same are disclosed. The multi bits flash memory device includes: a stacked structure including: a first active layer with a mesa-like form disposed on a substrate; a second active layer, having a different conductivity type from the first active layer, formed on the first active layer; an active interlayer isolation layer interposed between the first active layer and the second active layer such that the first active layer is electrically isolated from the second active layer; a common source and a common drain formed on a pair of opposite side surfaces of the stacked structure; a common first gate and a common second gate formed on the other pair of opposite side surfaces of the stacked structure; a tunnel dielectric layer interposed between the first and second gates and the first and second active layers; and a charge trap layer, storing charges that tunnel through the tunnel dielectric layer, interposed between the tunnel dielectric layer and the first and second gates.
摘要翻译：公开了一种多位闪存器件及其操作方法。多位闪存器件包括：堆叠结构，包括：设置在衬底上的具有台面状形状的第一有源层; 形成在所述第一有源层上的与所述第一有源层不同的导电类型的第二有源层; 插入在第一有源层和第二有源层之间的有源层间隔离层，使得第一有源层与第二有源层电隔离; 形成在所述堆叠结构的一对相对侧表面上的共同源极和共同漏极; 形成在所述堆叠结构的另一对相对侧表面上的公共第一栅极和公共第二栅极; 介于所述第一和第二栅极与所述第一和第二有源层之间的隧道介电层; 以及电荷捕获层，其存储穿过隧道介电层的电荷，介于隧道介电层和第一和第二栅极之间。

68. 发明申请

US20090091975A1 Non-volatile memory device and operation method of the same 有权
标题翻译：非易失性存储器件及其操作方法相同
公开(公告)号：US20090091975A1
公开(公告)日：2009-04-09
申请号：US12081679
申请日：2008-04-18
申请人： Tae-hee Lee , Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon
发明人： Tae-hee Lee , Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , H01L27/11521 , H01L27/11568
摘要： Provided are a non-volatile memory device and an operation method of the same. The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor.
摘要翻译：提供了一种非易失性存储器件及其操作方法。非易失性存储器件可以包括一个或多个主串，每个主弦可以包括可以分别包括多个存储单元晶体管的第一和第二子串; 以及电荷供给线，其可以被配置为向每个主串的第一和第二子串提供电荷或阻止电荷，其中每个主串可以包括第一接地选择晶体管，其可以连接到第一子串 ; 可以连接到第一接地选择晶体管的第一子串选择晶体管; 可以连接到第二子串的第二接地选择晶体管; 以及可以连接到第二接地选择晶体管的第二子串选择晶体管。

69. 发明申请

US20080157182A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080157182A1
公开(公告)日：2008-07-03
申请号：US11980632
申请日：2007-10-31
申请人： Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Won-joo Kim , June-mo Koo , Kyoung-Iae Cho , Jae-Woong Hyun , Sung-jae Byun
发明人： Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Won-joo Kim , June-mo Koo , Kyoung-Iae Cho , Jae-Woong Hyun , Sung-jae Byun
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/785 , H01L21/76897 , H01L29/41791 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/7851 , H01L29/7881 , H01L29/792 , H01L2029/7858
摘要： Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.
摘要翻译：示例性实施例涉及包括鳍型沟道区的半导体器件及其制造方法。半导体器件包括半导体衬底，半导体柱和接触插塞。半导体衬底包括至少一对使用（或功能）作为活性区的翅片。半导体柱可以插入翅片的部分之间以连接散热片。接触插塞可以设置（或形成）在半导体柱上并电连接到散热片的顶表面。

70. 发明申请

US20080157176A1 Nonvolatile memory device and method of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080157176A1
公开(公告)日：2008-07-03
申请号：US11902511
申请日：2007-09-21
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Sung-jae Byun
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Sung-jae Byun
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/42336 , H01L29/66803
摘要： A nonvolatile memory device having lower bit line contact resistance and a method of fabricating the same is provided. In the nonvolatile memory device, a semiconductor substrate of a first conductivity type may include first and second fins. A common bit line electrode may connect one end of the first fin to one end of the second fin. A plurality of control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins. A first string selection gate electrode may be positioned between the common bit line electrode and the plurality of control gate electrodes. The first string selection gate electrode may cover the first and second fins and expand across the top surface of each of the first and second fins. A second string selection gate electrode may be positioned between the first string selection gate electrode and the plurality of control gate electrodes. The second string selection gate electrode may cover the first and second fins and expand across the top surface of each of the first and second fins. The first fin under the first string selection gate electrode and the second fin under the second string selection gate electrode may have a second conductivity type opposite to the first conductivity type.
摘要翻译：提供一种具有较低位线接触电阻的非易失性存储器件及其制造方法。在非易失性存储器件中，第一导电类型的半导体衬底可以包括第一和第二鳍片。公共位线电极可将第一鳍片的一端连接到第二鳍片的一端。多个控制栅极电极可以覆盖第一和第二鳍片并且跨越第一和第二鳍片中的每一个的顶表面膨胀。第一串选择栅极可以位于公共位线电极和多个控制栅电极之间。第一串选择栅电极可以覆盖第一和第二鳍片并且横跨第一和第二鳍片中的每一个的顶表面扩展。第二串选择栅电极可以位于第一串选择栅电极和多个控制栅电极之间。第二串选择栅电极可以覆盖第一和第二鳍片并且横跨第一和第二鳍片中的每一个的顶表面扩展。第一串选择栅电极下的第一鳍和第二串选择栅电极下的第二鳍可以具有与第一导电类型相反的第二导电类型。

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