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61. 发明申请

US20070026155A1 Stain-proofing agent and building board using same 有权
标题翻译：防污剂和建筑板使用相同
公开(公告)号：US20070026155A1
公开(公告)日：2007-02-01
申请号：US11480410
申请日：2006-07-05
申请人： Masanori Ukai , Hiroyuki Yamauchi , Yasuhisa Imanishi
发明人： Masanori Ukai , Hiroyuki Yamauchi , Yasuhisa Imanishi
IPC分类号： C09D4/00 , C09K17/02
CPC分类号： C09D4/00 , C04B14/062 , C04B18/146 , C04B41/009 , C04B41/5089 , C04B41/52 , C04B41/68 , C04B41/71 , C04B2111/2038 , Y02W30/94 , Y02W30/97 , Y10T442/2279 , C04B41/46 , C04B2103/408 , C04B41/463 , C04B41/4876 , C04B41/502 , C04B41/483 , C04B41/522 , C04B18/26 , C04B28/18
摘要： An object of the present invention is to give durable excellent stain-proofing property to the surface of a coat formed on the surface of a substrate of a building board without deteriorating the surface of the coat. The present invention provides a stain-proofing agent which comprises silica fine particles, an aqueous solvent and, as a stain-proofing improver, an alkali metal compound and/or an alkaline earth metal compound and/or a phosphorus compound and/or a clay mineral. Furthermore, the present invention provides a building board having an excellent stain-proofing property prepared by applying a coating composition onto the surface of a substrate to form a coat, and then applying a stain-proofing agent onto the coat while the coat is in an unhardened state or applying a stain-proofing agent onto the coat after subjecting the coat to a roughening treatment to enhance the adhesion of the stain-proofing layer to the coat.
摘要翻译：本发明的一个目的是在建筑板的基板的表面上形成的涂层的表面上赋予持久的优异的防污性，而不会使涂层的表面变坏。本发明提供一种防污剂，其包含二氧化硅微粒，水性溶剂和作为防污改良剂的碱金属化合物和/或碱土金属化合物和/或磷化合物和/或粘土矿物。此外，本发明提供了一种建筑板，其具有通过将涂料组合物涂布在基材的表面上形成涂层而制备的优异的防污性，然后在外涂层上涂布防污剂未硬化状态，或者在对涂层进行粗糙化处理以增强防污层与涂层的粘附性之后，在涂层上施加防污剂。

62. 发明授权

US07136441B2 Clock recovery circuit 有权
公开(公告)号：US07136441B2
公开(公告)日：2006-11-14
申请号：US10038613
申请日：2002-01-08
申请人： Toru Iwata , Hiroyuki Yamauchi , Takefumi Yoshikawa
发明人： Toru Iwata , Hiroyuki Yamauchi , Takefumi Yoshikawa
IPC分类号： H04L7/00
CPC分类号： H04L25/45 , H03L7/0807 , H03L7/081 , H03L7/087 , H03L7/0891 , H04L7/033
摘要： A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.

63. 发明申请

US20060061395A1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US20060061395A1
公开(公告)日：2006-03-23
申请号：US10542727
申请日：2003-01-20
申请人： Takayuki Noto , Tomoru Sato , Hiroyuki Yamauchi
发明人： Takayuki Noto , Tomoru Sato , Hiroyuki Yamauchi
IPC分类号： H03B1/00
CPC分类号： H04L25/0278 , H03K5/086 , H03K17/08142 , H03K17/164 , H03K17/167 , H03K19/0005 , H04L25/0292
摘要： A semiconductor integrated circuit includes an input circuit for taking in signals and an output circuit for outputting signals. The input circuit is so set that the input impedance during input signal transition is lower than the input impedance on other occasions than input signal transition. The output circuit is so set that the driving force during the second half of signal transition is lower than the driving force during the first half of transition. Such setting that the input impedance during input signal transition is lower than the input impedance on other occasions than input signal transition reduces reflected waves during input signal transition. Such setting that the driving force during the second half of signal transition is lower than the driving force during the first half of transition suppresses production of reflected waves during the second half of signal transition. Thus, the necessity for external components, such as damping resistors and terminator resistors, for impedance matching is obviated.
摘要翻译：半导体集成电路包括用于接收信号的输入电路和用于输出信号的输出电路。输入电路设置为输入信号转换期间的输入阻抗低于输入信号转换时的输入阻抗。输出电路被设定为使得信号转换的后半段的驱动力低于转换前半部分的驱动力。在输入信号转换期间，输入信号转换期间的输入阻抗比其他情况下的输入阻抗低于输入信号转换的设置会降低输入信号转换期间的反射波。在信号转换的后半期间的驱动力比转换的前半部分的驱动力低的设定在信号转换的后半期间抑制了反射波的产生。因此，消除了用于阻抗匹配的诸如阻尼电阻器和终端电阻器的外部组件的必要性。

64. 发明申请

US20050264422A1 IC tag communication relay device, IC tag communication relay method 有权
标题翻译： IC标签通信中继装置，IC标签通信中继方式
公开(公告)号：US20050264422A1
公开(公告)日：2005-12-01
申请号：US11000206
申请日：2004-12-01
申请人： Toshio Watanabe , Hiroyuki Yamauchi
发明人： Toshio Watanabe , Hiroyuki Yamauchi
IPC分类号： B65G57/00 , G06K7/08 , G06K7/10 , G06K17/00 , G08B13/14 , H04B1/59 , H04B5/02
CPC分类号： G06K19/07771 , G06K7/10178 , G06K7/10336
摘要： An IC tag communication relay device is provided with an antenna section, lead lines and input/output unit. The antenna section is equipped with one or more antennas for transmitting and receiving electromagnetic radiation to and from IC tags. The lead lines are connected to each antenna for transmitting electrical signals corresponding to transmitted and received electromagnetic radiation. The input/output unit is arranged outside of the antenna corresponding to each antenna connected to the lead lines.
摘要翻译： IC标签通信中继装置设置有天线部分，引线和输入/输出单元。天线部分配备有一个或多个天线，用于向IC标签发送和接收电磁辐射。导线连接到每个天线，用于发送对应于发射和接收的电磁辐射的电信号。输入/输出单元布置在与连接到引线的每个天线对应的天线的外部。

65. 发明申请

US20050254280A1 Mask ROM 有权
标题翻译：面具ROM
公开(公告)号：US20050254280A1
公开(公告)日：2005-11-17
申请号：US11121135
申请日：2005-05-04
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G11C17/12 , G11C17/00 , H01L21/8246 , H01L27/112
CPC分类号： G11C17/12 , H01L27/112
摘要： A mask ROM includes bit lines, word lines intersecting with the bit lines and bit cells provided along the word lines, each of the bit lines being formed of a cell transistor having a gate connected to an associated one of the word lines. In the mask ROM, further provided is a source node commonly connected to respective sources of ones of the cell transistors having a gate connected to one of adjacent two word lines. A current flows from a selected bit line to a non-selected bit line via a cell transistor selected in reading out data and the source node.
摘要翻译：掩模ROM包括位线，与位线相交的字线和沿着字线提供的位单元，每个位线由具有连接到相关联的字线之一的栅极的单元晶体管形成。在掩模ROM中，进一步提供了一个源节点，其通常连接到具有连接到相邻两个字线中的一个的栅极的一个单元晶体管的各个源极。 A电流通过在读出数据和源节点中选择的单元晶体管从选定的位线流向未选择的位线。

66. 发明申请

US20050219921A1 Semiconductor system 有权
标题翻译：半导体系统
公开(公告)号：US20050219921A1
公开(公告)日：2005-10-06
申请号：US11097359
申请日：2005-04-04
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G11C11/413 , G11C5/14 , G11C7/00 , G11C8/08 , G11C16/06
CPC分类号： G11C5/145 , G11C8/08
摘要： A semiconductor system includes a plurality of memory systems (SARM, ROM, etc.) and circuit systems. The semiconductor system further includes an analog power supply circuit which is common to the memory systems. The analog power supply circuit supplies a source potential to word line drivers of the memory systems. The source potential is set to a potential different from a ground potential and a supply voltage of the semiconductor system.
摘要翻译：半导体系统包括多个存储器系统（SARM，ROM等）和电路系统。半导体系统还包括对于存储器系统是共同的模拟电源电路。模拟电源电路为存储器系统的字线驱动器提供源极电位。源极电位被设定为与半导体系统的接地电位和电源电压不同的电位。

67. 发明申请

US20050174870A1 SRAM device 审中-公开
公开(公告)号：US20050174870A1
公开(公告)日：2005-08-11
申请号：US11101467
申请日：2005-04-08
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G11C7/00 , G11C11/00 , G11C11/40 , G11C11/407 , H01L21/8244 , H01L27/11
CPC分类号： H01L27/1104
摘要： In a CMOS type SRAM device having a 6-transistor configuration, only a drive transistor and an access transistor of one unit circuit are designed with a larger size, with the other four transistors having a smaller size.

68. 再颁专利

USRE38647E1 Sense amplifier circuit 有权
标题翻译：感应放大电路
公开(公告)号：USRE38647E1
公开(公告)日：2004-11-09
申请号：US09945603
申请日：2001-09-04
申请人： Hiroyuki Yamauchi , Toshio Yamada
发明人： Hiroyuki Yamauchi , Toshio Yamada
IPC分类号： G01R1900
CPC分类号： G11C7/065 , H03K17/102 , H03K17/145
摘要： In order to enhance the sensitivity of a sense amplifier circuit, each one of the transistor pair composing the sense amplifier circuit is formed by transistors connected parallel in an even number of stages, and therefore the sense amplifier circuit is made of transistor pair having an extremely balanced characteristic, cancelling the asymmetricity of current-voltage characteristic of the transistor pair to null.

69. 发明授权

US06728148B2 Programmed value determining circuit, semiconductor integrated circuit device including the same, and method for determining programmed value 失效
标题翻译：编程值确定电路，包括其的半导体集成电路器件以及用于确定编程值的方法
公开(公告)号：US06728148B2
公开(公告)日：2004-04-27
申请号：US10232785
申请日：2002-08-28
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G11C700
CPC分类号： G11C17/143 , G11C17/14 , G11C17/18
摘要： A programmed value determining circuit is provided in which both the area of the programmable element and the leak current are reduced. During the first period after power is turned on, both the PMOS transistor Qp1 and the NMOS transistor Qn1 are turned off, and the storage node is disconnected from the power line VDD and the ground line VSS. During the second period after the first period, at least the NMOS transistor Qn1 is turned on, the storage node is connected to the ground line VSS via the program element 10, and the state of the storage node is detected by the detecting portion 11. During the third period after the second period, the PMOS transistor Qp1 and the NMOS transistor Qn1 are turned off, and the state of the storage node is held by the latch portion 12.
摘要翻译：提供了编程值确定电路，其中可编程元件的面积和漏电流均减小。在电源接通之后的第一时段期间，PMOS晶体管Qp1和NMOS晶体管Qn1都截止，并且存储节点与电源线VDD和接地线VSS断开。在第一时段之后的第二周期期间，至少NMOS晶体管Qn1导通，存储节点经由编程元件10连接到接地线VSS，并且由检测部分11检测存储节点的状态。在第二周期之后的第三周期期间，PMOS晶体管Qp1和NMOS晶体管Qn1截止，存储节点的状态由锁存部12保持。

70. 发明授权

US06373759B1 SRAM device 有权
公开(公告)号：US06373759B1
公开(公告)日：2002-04-16
申请号：US09823102
申请日：2001-03-30
申请人： Hiroyuki Yamauchi
发明人： Hiroyuki Yamauchi
IPC分类号： G11C700
摘要： An SRAM device includes: a plurality of normal memory blocks each including N normal memory cells for storing data, wherein N is a natural number; a spare memory block including one or more spare memory cells for storing data; a defective block setting section for storing first defective block information indicating a normal memory block including a defective normal memory cell among the plurality of normal memory blocks; N internal data lines which are respectively coupled to the N normal memory cells included in each of the plurality of normal memory blocks, where the N internal data lines are used for reading data stored in the N normal memory cells included in one of the plurality of normal memory blocks which is designated by access information, wherein the access information is externally input to the SRAM device; one or more spare data lines coupled to the spare memory block for reading data from the one or more spare memory cells included in the spare memory block; N external data lines via which the SRAM device outputs the data; and a coupling circuit for, depending on whether or not the first defective block information matches the access information, either coupling those of the N internal data lines which are not coupled to a defective normal memory cell in the normal memory block indicated by the first defective block information and at least one of the one or more spare data lines to the N external data lines, or coupling the N internal data lines to the N external data lines.

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