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61. 发明授权

US07710482B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07710482B2
公开(公告)日：2010-05-04
申请号：US11818292
申请日：2007-06-14
申请人： Hiroaki Takasu
发明人： Hiroaki Takasu
IPC分类号： H04N3/14 , H04N5/335
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14643
摘要： A MOS image sensor IC has a silicon substrate, a MOS transistor and photodiodes disposed on the silicon substrate, and pixel regions each comprising one of the photodiodes. A protective film is disposed around the pixel regions. A first conductor for potential fixation is disposed under the protective film and surrounds the pixel regions. The first conductor is electrically fixed to a potential of the silicon substrate.
摘要翻译： MOS图像传感器IC具有硅衬底，MOS晶体管和设置在硅衬底上的光电二极管，以及每个包括一个光电二极管的像素区域。保护膜设置在像素区域周围。用于电位固定的第一导体设置在保护膜下方并且围绕像素区域。第一导体电固定到硅衬底的电位。

62. 发明申请

US20090152633A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20090152633A1
公开(公告)日：2009-06-18
申请号：US12315635
申请日：2008-12-04
申请人： Hiroaki Takasu , Sukehiro Yamamoto
发明人： Hiroaki Takasu , Sukehiro Yamamoto
IPC分类号： H01L29/78
CPC分类号： H01L21/823475 , H01L21/823418 , H01L24/05 , H01L27/0266 , H01L29/4238 , H01L2224/02166 , H01L2224/05093 , H01L2224/05556 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： In a semiconductor device including, between an external connection terminal and an internal circuit region, an NMOS transistor for ESD protection having a gate potential fixed to a ground potential, the external connection terminal is formed above a drain region of the NMOS transistor for ESD protection, and the drain region is surrounded by a source region through a channel region. Further, the drain region has a shape with rounded corners in plan view.
摘要翻译：在包括在外部连接端子和内部电路区域之间的半导体器件中，具有固定在接地电位上的栅极电位的用于ESD保护的NMOS晶体管，外部连接端子形成在用于ESD保护的NMOS晶体管的漏极区域之上并且漏极区域被源区域通过沟道区域包围。此外，漏极区域在平面图中具有圆角。

63. 发明授权

US07535240B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07535240B2
公开(公告)日：2009-05-19
申请号：US11818123
申请日：2007-06-13
申请人： Hiroaki Takasu , Sukehiro Yamamoto
发明人： Hiroaki Takasu , Sukehiro Yamamoto
IPC分类号： G01R31/02 , G01R31/26 , G01R11/18
CPC分类号： H01L23/544 , G01R31/2884 , G01R31/2887 , H01L2223/5446 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface of a tip of a probing needle used for carrying out an electrical measurement of IC chips; and the patterns for detecting displacement at probing are provided in a pair for each of the IC chips.
摘要翻译：提供一种半导体器件，其中：用于检测探测位移的图案由形成在保护膜下面的多个微小导体形成; 形成在保护膜下方的多个微导体中的每一个电绝缘并形成为小于用于执行IC芯片的电测量的探针的尖端的底表面; 并且针对每个IC芯片成对地设置用于检测探测位移的图案。

64. 发明申请

US20090101973A1 Field effect transistor formed on an insulating substrate and integrated circuit thereof 有权
标题翻译：形成在绝缘基板上的场效应晶体管及其集成电路
公开(公告)号：US20090101973A1
公开(公告)日：2009-04-23
申请号：US11975923
申请日：2007-10-22
申请人： Yutaka Hayashi , Hisashi Hasegawa , Hiroaki Takasu , Jun Osanai
发明人： Yutaka Hayashi , Hisashi Hasegawa , Hiroaki Takasu , Jun Osanai
IPC分类号： H01L29/78
CPC分类号： H01L29/78615 , H01L29/66772
摘要： A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. The third region and the second region are in contact with each other and make a low resistance junction. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode. One of the first and the fourth regions is used as an output region according to a circuit operation.
摘要翻译：场效应晶体管具有绝缘基板，形成在绝缘基板上的半导体薄膜和半导体薄膜上的栅极绝缘膜。在栅极绝缘膜上形成第一栅电极。在第一栅电极的长度方向的相对侧的半导体膜的表面上或表面上形成具有第一导电类型的第一区域和第二区域。具有与第一导电类型相反的第二导电类型的第三区域与第一栅电极的宽度方向上的第二区域并排设置在半导体膜上或半导体膜中。第三区域和第二区域彼此接触并形成低电阻结。第二栅电极沿着第二区形成在栅极绝缘膜上。具有第一导电类型的第四区域形成在第二区域的相对于第二栅电极的相反侧上或半导体膜中。根据电路操作将第一和第四区域中的一个用作输出区域。

65. 发明申请

US20090039431A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090039431A1
公开(公告)日：2009-02-12
申请号：US12184585
申请日：2008-08-01
申请人： Hiroaki Takasu
发明人： Hiroaki Takasu
IPC分类号： H01L27/088
CPC分类号： H01L21/82345 , H01L21/823412 , H01L21/823842 , H01L27/0266 , H01L27/088 , H01L27/092
摘要： Provided is a semiconductor device, including: an N-type MOS transistor for an internal element and a P-type MOS transistor for an internal element both provided in an internal circuit region; and an N-type MOS transistor for ESD protection provided between an external connection terminal and the internal circuit region, in which a gate electrode of the N-type MOS transistor for ESD protection is formed of P-type polysilicon.
摘要翻译：提供一种半导体器件，包括：内部元件的N型MOS晶体管和用于内部元件的P型MOS晶体管，其均设置在内部电路区域中; 以及用于ESD保护的N型MOS晶体管，其设置在外部连接端子和内部电路区域之间，其中用于ESD保护的N型MOS晶体管的栅电极由P型多晶硅形成。

66. 发明申请

US20080150070A1 Image sensor IC 审中-公开
标题翻译：图像传感器IC
公开(公告)号：US20080150070A1
公开(公告)日：2008-06-26
申请号：US12004157
申请日：2007-12-19
申请人： Hiroaki Takasu
发明人： Hiroaki Takasu
IPC分类号： H01L31/0224
CPC分类号： H01L27/14601 , H01L27/14692
摘要： Provided is an image sensor IC in which a conductive material transmissive to light, which is fixed to the same potential, is formed under a protection film in a plurality of pixel regions. The conductive material transmissive to light for potential fixation is formed in each pixel, has a narrow and linear shape, and is electrically connected so as to hold the same potential as a potential of a silicon substrate. Accordingly, a potential of each of the regions which become a base at the time of forming the protective film is kept constant in an entire pixel region, thereby obtaining a uniform thickness and quality of the protective film. As a result, variation in photoelectric conversion characteristic of the pixels can be eliminated.
摘要翻译：提供了一种图像传感器IC，其中在多个像素区域中的保护膜下面形成有透光的导电材料，该导电材料固定在相同的电位上。在每个像素中形成用于电位固定的透射光的导电材料，具有窄且直线的形状，并被电连接以便保持与硅衬底的电位相同的电位。因此，在形成保护膜时，成为基底的每个区域的电位在整个像素区域中保持恒定，从而获得均匀的厚度和保护膜的质量。结果，可以消除像素的光电转换特性的变化。

67. 发明申请

US20060033164A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060033164A1
公开(公告)日：2006-02-16
申请号：US11199292
申请日：2005-08-08
申请人： Hiroaki Takasu
发明人： Hiroaki Takasu
IPC分类号： H01L23/62
CPC分类号： H01L27/0629 , H01L27/0738 , H01L28/20
摘要： Provided is a semiconductor device having a semiconductor integrated circuit formed on an SOI substrate, in which a bleeder resistor is formed of a single-crystal-silicon device-forming layer, and an upper electrode for resistance fixation is formed over the bleeder resistor and on a thin oxide film and is fixed to the identical potential as that of the bleeder resistor located below the electrode. Further, an impurity diffusion region is formed on the silicon substrate, and is fixed to the identical potential as that of the bleeder resistor above the impurity diffusion region. In addition, those three elements; the upper electrode for resistance fixation, the bleeder resistor, and the lower impurity diffusion region are collectively and electrically connected with one another through a conductor filling a contact hole for potential fixation.
摘要翻译：提供了一种半导体器件，其具有形成在SOI衬底上的半导体集成电路，其中泄放电阻器由单晶硅器件形成层形成，并且用于电阻固定的上电极形成在泄放电阻器上并在其上薄的氧化膜并被固定到与位于电极下方的泄放电阻器相同的电位。此外，在硅衬底上形成杂质扩散区，并将其固定为与杂质扩散区上方的泄放电阻相同的电位。另外，这三个要素; 用于电阻固定的上电极，泄放电阻器和下杂质扩散区域通过填充用于电位固定的接触孔的导体而彼此共同且电连接。

68. 发明授权

US06566721B2 Semiconductor device 有权
公开(公告)号：US06566721B2
公开(公告)日：2003-05-20
申请号：US09998815
申请日：2001-10-19
申请人： Hiroaki Takasu
发明人： Hiroaki Takasu
IPC分类号： H01L2976
CPC分类号： H01L27/0802 , H01L23/5228 , H01L29/8605 , H01L2924/0002 , H01L2924/00
摘要： It is intended to provide a semiconductor device in which a fuse required conventionally is omitted and an initial resistance value can be maintained even under stress imposed due to packaging or the like, a high-accuracy bleeder resistance circuit that can maintain an accurate voltage division ratio, and a high-accuracy semiconductor device with such a bleeder resistance circuit, for example, a voltage detector or a voltage regulator. In a semiconductor device with a resistor, the resistor includes a P-type resistor made of a P-type semiconductor and an N-type resistor made of an N-type semiconductor which are combined to form one body, and the P-type resistor and the N-type resistor are placed on low and high potential sides, respectively. The P-N junction is irradiated with a laser beam or the like, whereby rectification is damaged to allow conduction.

69. 发明授权

US08445983B2 Semiconductor device for performing photoelectric conversion 有权
标题翻译：用于执行光电转换的半导体器件
公开(公告)号：US08445983B2
公开(公告)日：2013-05-21
申请号：US13136004
申请日：2011-07-20
申请人： Atsushi Iwasaki , Hiroaki Takasu
发明人： Atsushi Iwasaki , Hiroaki Takasu
IPC分类号： H01L27/14
CPC分类号： H01L27/14689 , H01L27/1463 , H01L27/14643
摘要： A semiconductor device for performing photoelectric conversion of incident light includes a substrate and a well region having different conductivity types. A depletion layer is generated in a vicinity of a junction interface between the substrate and the well region. A first trench has a depth equal to a height up to a top portion of the depletion layer generated on a bottom side of the well region and a width extending to a heavily doped region formed in the well region. A second trench has a depth larger than that of a portion of the depletion layer generated on the bottom side of the well region and a width larger than that of portions of the depletion layer generated on the sides of the well region. The second trench surrounds the first trench so as to confine the depletion layer under the first trench except for a region thereof under the heavily doped region. An insulator is buried into each the first trench and the second trench.
摘要翻译：用于进行入射光的光电转换的半导体器件包括基板和具有不同导电类型的阱区域。在衬底和阱区之间的接合界面附近产生耗尽层。第一沟槽的深度等于在阱区的底侧上产生的耗尽层的顶部的高度，以及延伸到在阱区中形成的重掺杂区的宽度。第二沟槽的深度大于在阱区底部产生的耗尽层的一部分的深度，并且其宽度大于在阱区域的侧面上产生的耗尽层的部分的宽度。第二沟槽围绕第一沟槽，以将耗尽层限制在第一沟槽之下，除了在重掺杂区域之下的区域之外。绝缘体被埋入每个第一沟槽和第二沟槽中。

70. 发明授权

US08278714B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08278714B2
公开(公告)日：2012-10-02
申请号：US12924263
申请日：2010-09-23
申请人： Hiroaki Takasu
发明人： Hiroaki Takasu
IPC分类号： H01L21/00
CPC分类号： H01L27/0266 , H01L29/0895
摘要： A semiconductor device has an external connection terminal, an internal circuit region, an ESD protection N-MOS transistor provided between the external connection terminal and the internal circuit region to protect an internal element formed in the internal circuit region, and a shallow trench structure provided to isolate the ESD protection N-MOS transistor. A thin insulating film is formed on a drain region of the ESD protection N-MOS transistor. An electrode is disposed above the drain region and on the thin insulating film for receiving a signal from the external connection terminal. The thin insulating film has a film thickness and film properties that allow dielectric breakdown and establish conduction between the electrode and the drain region when a voltage exceeding an absolute maximum rating of the semiconductor device is applied to the electrode.
摘要翻译：半导体器件具有外部连接端子，内部电路区域，设置在外部连接端子和内部电路区域之间的ESD保护N-MOS晶体管，以保护形成在内部电路区域中的内部元件，以及提供浅沟槽结构隔离ESD保护N-MOS晶体管。在ESD保护N-MOS晶体管的漏极区域上形成薄的绝缘膜。电极设置在漏极区域上方和薄绝缘膜上，用于接收来自外部连接端子的信号。当超过绝缘最大额定值的电压被施加到电极时，薄的绝缘膜具有允许电介质击穿并且在电极和漏极区域之间建立导电的膜厚度和膜特性。

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