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61. 发明授权

US5671394A Microcomputer having ROM data protection function 失效
标题翻译：微电脑具有ROM数据保护功能
公开(公告)号：US5671394A
公开(公告)日：1997-09-23
申请号：US313534
申请日：1994-09-27
申请人： Hiroshi Katsuta
发明人： Hiroshi Katsuta
IPC分类号： G06F11/22 , G06F11/14 , G06F12/14 , G06F21/00 , G06F21/24 , G11C29/52
CPC分类号： G11C29/52 , G06F21/79
摘要： A single-chip microcomputer includes a program ROM storing a program; a central processing unit executing the program read out from the program ROM for performing data processing; an external data input port for receiving data to be processed by the central processing unit, from an external device; and an external data output port for outputting data processed by the central processing unit to an external device. The program ROM also stores a test program for testing the program ROM and a plurality of bytes of collation information. The central processing unit has a test mode for executing the test program, and compares the plurality of bytes of collation information with a corresponding number of bytes of data sequentially input through the external input port. The central processing unit selects one of the plurality of bytes of collation information and compares the selected byte of collation information with one byte of data input through the external input port when the selected byte of collation information is selected. Only when the plurality of bytes of collation information are consistent with all the bytes of data sequentially inputted through the external input port will the central processing unit allow contents stored in the program ROM to be output through the external output port.
摘要翻译：单片微计算机包括存储程序的程序ROM; 执行从用于执行数据处理的程序ROM读出的程序的中央处理单元; 外部数据输入端口，用于从外部设备接收要由中央处理单元处理的数据; 以及用于将由中央处理单元处理的数据输出到外部设备的外部数据输出端口。程序ROM还存储用于测试程序ROM的测试程序和多个对比信息字节。中央处理单元具有用于执行测试程序的测试模式，并将核对信息的多个字节与通过外部输入端口顺序输入的相应数量的数据字节进行比较。中央处理单元选择多个字节的对照信息中的一个，并且当所选择的核对信息的所选字节被选择时，比较所选择的核对信息字节与通过外部输入端口输入的数据的一个字节。仅当核对信息的多个字节与通过外部输入端口顺序输入的数据的所有字节一致时，中央处理单元才允许存储在程序ROM中的内容通过外部输出端口输出。

62. 发明授权

US5386519A Information processing apparatus incorporating buffer storing a plurality of branch target instructions for branch instructions and interrupt requests 失效
标题翻译：信息处理装置，包括缓冲器，存储用于分支指令和中断请求的多个转移目标指令
公开(公告)号：US5386519A
公开(公告)日：1995-01-31
申请号：US917286
申请日：1992-07-23
申请人： Takanori Nakamura , Hiroshi Katsuta
发明人： Takanori Nakamura , Hiroshi Katsuta
IPC分类号： G06F9/28 , G06F9/32 , G06F9/38 , G06F9/26 , G06F9/30 , G06F9/42
CPC分类号： G06F9/3808 , G06F9/3861
摘要： An information processing apparatus is provided with a buffer and accompanying circuitry for retrieving instruction code at a branch target address and providing that code to an execution unit within a single clock, much more quickly than the one bus cycle which has been required previously. Not only branches, but also interrupts may be handled with this relatively simple hardware, making the invention useful in the control field, among other applications. The buffer circuitry can store a plurality of branch target addresses and/or interrupt addresses.
摘要翻译：信息处理装置设置有缓冲器和伴随的电路，用于在分支目标地址处检索指令代码，并将该代码提供给单个时钟内的执行单元，比先前需要的一个总线周期快得多。不仅可以使用这种相对简单的硬件来处理分支，还可以处理中断，使本发明在控制领域以及其他应用中有用。缓冲电路可以存储多个分支目标地址和/或中断地址。

63. 发明授权

US5274831A Microprocessor in response to an interrupt request for executing a microinstruction for sampling the mode of operation 失效
标题翻译：微处理器响应于执行用于对操作模式进行采样的微指令的中断请求
公开(公告)号：US5274831A
公开(公告)日：1993-12-28
申请号：US447290
申请日：1989-12-07
申请人： Hiroshi Katsuta
发明人： Hiroshi Katsuta
IPC分类号： G06F9/22 , G06F9/318 , G06F9/455 , G06F9/48 , G06F9/46 , G06F9/00
CPC分类号： G06F9/4812 , G06F9/30174 , G06F9/30189 , G06F9/45533
摘要： A microprocessor having two different modes of operation includes a mode flag which designates one of the two operation modes of the microprocessor, and a central processing unit which executes a program in one of the two operation modes designated by the mode flag. The central processing unit includes a microprogram memory which stores an interrupt initiation microprogram, an output device which is responsive to an interrupt request for reading out the interrupt initiation microprogram from the microprogram memory and a circuit for executing the interrupt initiation microprogram to generate a sampling signal. A mode terminal is provided, which is supplied with operation mode information. A circuit responsive to the sampling signal samples a logic level of the operation mode information at the mode terminal. A circuit is provided, which is responsive to the sampled logic level from the sampling circuit in order to bring the mode flag into one of set and reset states of the mode flag designation.
摘要翻译：具有两种不同操作模式的微处理器包括指定微处理器的两种操作模式之一的模式标志，以及以模式标志指定的两种操作模式之一执行程序的中央处理单元。中央处理单元包括存储中断启动微程序的微程序存储器，响应于从微程序存储器读出中断启动微程序的中断请求的输出装置和用于执行中断启动微程序以生成采样信号的电路。提供了模式终端，其提供有操作模式信息。响应于采样信号的电路在模式终端处采样操作模式信息的逻辑电平。提供电路，其响应于来自采样电路的采样逻辑电平，以将模式标志置于模式标志指定的设置和复位状态之一。

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