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61. 发明申请

US20050128851A1 Data storage device and refreshing method for use with such device 有权
标题翻译：数据存储装置和与这种装置一起使用的刷新方法
公开(公告)号：US20050128851A1
公开(公告)日：2005-06-16
申请号：US11048387
申请日：2005-02-01
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C11/404 , G11C11/406 , G11C7/00
CPC分类号： G11C11/406 , G11C11/404 , G11C2211/4016 , G11C2211/4065 , G11C2211/4068 , H01L2924/15311
摘要： A data storage device such as a DRAM memory having a plurality of data storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which varies with time and represents one of two binary logic states. A selection circuit 16, writing circuits 18 and a refreshing circuit 22 apply input signals to the data storage cells to reverse the variation of the physical parameter with time of at least those cells representing one of the binary logic states by causing a different variation in the physical parameter of cells in one of said states than in the other.
摘要翻译：公开了诸如具有多个数据存储单元10的DRAM存储器的数据存储装置。每个数据存储单元10具有随时间变化并表示两个二进制逻辑状态之一的物理参数。选择电路16，写入电路18和刷新电路22将输入信号施加到数据存储单元，以通过使代表二进制逻辑状态之一的那些单元的至少那些单元的时间的时间来反转物理参数的变化，在所述状态之一的细胞的物理参数比在另一个状态。

62. 发明授权

US06873539B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06873539B1
公开(公告)日：2005-03-29
申请号：US10727742
申请日：2003-12-04
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G01T1/24 , G11C11/403 , G11C11/404 , H01L21/8242 , H01L27/108 , H01L29/786 , H01L31/10 , G11C11/24
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.
摘要翻译：公开了诸如存储器件或辐射检测器的半导体器件，其中在衬底上形成数据存储单元。每个数据存储单元包括具有源极，漏极和栅极的场效应晶体管，以及布置在源极和漏极之间的用于存储在体内产生的电荷的主体。体内净电荷的大小可以通过施加到晶体管的输入信号来调节，并且可以通过在栅极和漏极之间施加电压信号来至少部分地抵消由输入信号调节净电荷在源和漏之间。

63. 发明申请

US20050017240A1 Integrated circuit device, and method of fabricating same 有权
标题翻译：集成电路器件及其制造方法
公开(公告)号：US20050017240A1
公开(公告)日：2005-01-27
申请号：US10884481
申请日：2004-07-02
申请人： Pierre Fazan
发明人： Pierre Fazan
IPC分类号： H01L21/8239 , H01L21/8242 , H01L21/84 , H01L27/105 , H01L27/108 , H01L27/12 , H01L29/786 , H01L29/04
CPC分类号： H01L27/10894 , H01L21/845 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/10802 , H01L27/10823 , H01L27/10826 , H01L27/10844 , H01L27/10897 , H01L27/1211 , H01L29/7841 , H01L29/785
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to integrated circuit device including SOI logic transistors and SOI memory transistors, and method for fabricating such a device. In one embodiment, integrated circuit device includes memory portion having, for example, PD or FD SOI memory cells, and logic portion having, for example, high performance transistors, such as Fin-FET, multiple gate transistors, and/or non-high performance transistors (such as single gate transistors that do not possess the performance characteristics of the high performance transistors).
摘要翻译：这里描述和说明了许多发明。在第一方面，本发明涉及包括SOI逻辑晶体管和SOI存储晶体管的集成电路器件及其制造方法。在一个实施例中，集成电路器件包括具有例如PD或FD SOI存储器单元的存储器部分和具有例如诸如Fin-FET，多个栅极晶体管和/或非高电压的高性能晶体管的逻辑部分性能晶体管（例如不具有高性能晶体管的性能特性的单栅极晶体管）。

64. 发明授权

US06274423B1 Etch process for aligning a capacitor structure and an adjacent contact corridor 有权
标题翻译：用于对齐电容器结构和相邻触点走廊的蚀刻工艺
公开(公告)号：US06274423B1
公开(公告)日：2001-08-14
申请号：US09236761
申请日：1999-01-25
申请人： Kirk D. Prall , Pierre Fazan , Trung Doan , Tyler Lowrey
发明人： Kirk D. Prall , Pierre Fazan , Trung Doan , Tyler Lowrey
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10808
摘要： An etch process for increasing the alignment tolerances between capacitor components and an adjacent contact corridor in Dynamic Random Access Memories. The etch process is implemented in a capacitor structure formed over a semiconductor substrate The capacitor structure includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. The second conductor has a horizontal region laterally adjacent to and extending away from the first conductor. The etch process comprises the steps of: (a) forming a layer of patterned photoresist over the second conductor, the photoresist being patterned to expose a portion of the horizontal region of the second conductor at a desired location of a contact corridor above a source/drain region in the substrate; (b) using the photoresist as an etch mask, anisotropically etching away the exposed portions of the horizontal region of the second conductor; and (c) using the photoresist again as an etch mask, isotropically etching away substantially all of the remaining portions of the horizontal region of the second conductor and thereby enlarging the area available for locating the contact corridor. Alternatively, the horizontal region of the second conductor is removed using a single isotropic etch.
摘要翻译：用于增加动态随机存取存储器中电容器组件与相邻触点走廊之间的对准公差的蚀刻工艺。该蚀刻工艺在形成于半导体衬底上的电容器结构中实施。电容器结构包括第一导体，第一导体上的电介质层和介电层上的第二导体。第二导体具有横向邻近并远离第一导体延伸的水平区域。蚀刻工艺包括以下步骤：（a）在第二导体上形成图案化光致抗蚀剂层，光刻胶被图案化以在第二导体的水平区域的一个源/ 漏极区域; （b）使用光致抗蚀剂作为蚀刻掩模，各向异性地蚀刻掉第二导体的水平区域的暴露部分; 和（c）再次使用光致抗蚀剂作为蚀刻掩模，各向同性地蚀刻掉第二导体的水平区域的基本上所有其余部分，从而扩大可用于定位接触走廊的面积。或者，使用单个各向同性蚀刻去除第二导体的水平区域。

65. 发明授权

US6002149A Capacitor structures for memory cells 失效
标题翻译：记忆细胞的电容结构
公开(公告)号：US6002149A
公开(公告)日：1999-12-14
申请号：US554546
申请日：1995-11-07
申请人： Charles Dennison , Pierre Fazan
发明人： Charles Dennison , Pierre Fazan
IPC分类号： H01L27/108
CPC分类号： H01L27/10817
摘要： A three dimensional capacitor structure particularly adapted for use as a memory cell capacitor of a DRAM is disclosed. The capacitor structure incorporates the substantially vertical (in relation to the substrate) sides of a plurality of spacers into the storage node capacitor to increase the total area of the storage node capacitor. In the described embodiments of the invention, a first spacer and a second spacer are formed next to the digit lines. The bottom storage node plate is formed on at least the first sides of the spacers to increase area of the storage node. The bottom storage node plate is also formed on the upper surface of the digit line. Additional spacers can also be added to further increase the area of the storage node. A dielectric layer is formed over the first capacitor plate and a second capacitor plate layer is formed over the dielectric layer to complete the structure.
摘要翻译：公开了一种特别适用于DRAM的存储单元电容器的三维电容器结构。电容器结构将多个间隔物的基本垂直（相对于衬底）侧面结合到存储节点电容器中，以增加存储节点电容器的总面积。在本发明的所述实施例中，第一间隔件和第二间隔件形成在数字线的旁边。底部存储节点板形成在间隔物的至少第一侧上以增加存储节点的面积。底部存储节点板也形成在数字线的上表面上。还可以添加附加的间隔物以进一步增加存储节点的面积。在第一电容器板上形成电介质层，在电介质层上方形成第二电容器板层以完成该结构。

66. 发明授权

US5187638A Barrier layers for ferroelectric and pzt dielectric on silicon 失效
标题翻译：用于铁电的阻挡层和硅上的pzt电介质
公开(公告)号：US5187638A
公开(公告)日：1993-02-16
申请号：US919671
申请日：1992-07-27
申请人： Gurtej S. Sandhu , Pierre Fazan
发明人： Gurtej S. Sandhu , Pierre Fazan
IPC分类号： H01L21/02 , H01L21/285 , H01L27/108 , H01L27/115 , H01L29/92
CPC分类号： H01L27/11502 , H01L27/10808 , H01L28/75 , H01L21/28568 , H01L28/55
摘要： The present invention introduces an effective way to produce a thin film capacitor utilizing a high dielectric constant material for the cell dielectric through the use of a single transition metal, such as Molybdenum, for a bottom plate electrode which oxidizes to form a highly conducting oxide. Using Molybdenum, for example, will make a low resistive contact to the underlying silicon since Molybdenum reacts with silicon to form MoSix with low (
摘要翻译：本发明通过使用单一过渡金属（例如钼）制造用于电介质的高介电常数材料的薄膜电容器用于氧化形成高导电氧化物的底板电极的有效方法。例如，使用钼将会与下面的硅形成低电阻接触，因为钼与硅反应以形成具有低（<500μm欧姆 - 厘米）体积电阻的MoSix。此外，Mo / MoSix与现在的ULSI工艺流程兼容或者制造DRAM等。

67. 发明授权

US5130885A Dram cell in which a silicon-germanium alloy layer having a rough surface morphology is utilized for a capacitive surface 失效
标题翻译：其中具有粗糙表面形态的硅锗合金层用于电容表面的电池
公开(公告)号：US5130885A
公开(公告)日：1992-07-14
申请号：US727701
申请日：1991-07-10
申请人： Pierre Fazan , Gurtej S. Sandhu
发明人： Pierre Fazan , Gurtej S. Sandhu
IPC分类号： H01L27/108
CPC分类号： H01L27/10808
摘要： A dynamic random access memory cell in which a silicon-germanium alloy layer having a rough surface morphology is utilized for the capacitive surface of the storage-node plate of the cell capacitor. To create a DRAM array having such cells, a silicon-germanium alloy is deposited, typically via rapid thermal chemical vapor deposition, on top of a single crystalline silicon or polycrystalline silicon storage-node plate layer under conditions which favor three-dimensional growth in the form of macroscopic islanding (i.e., a high concentration of germanium in precursor gases and relatively high deposition temperature). A cell dielectric layer, which exhibits the property of bulk-limited conduction (e.g., silicon nitride), is utilized. Except for the deposition of the silicon-germanium alloy, array processing is conventional.
摘要翻译：具有粗糙表面形态的硅 - 锗合金层用于电池电容器的存储节点板的电容表面的动态随机存取存储单元。为了形成具有这样的单元的DRAM阵列，通常通过快速热化学气相沉积在单晶硅或多晶硅存储节点板层的顶部上沉积硅 - 锗合金，在有利于三维生长的条件下宏观孤岛的形式（即前体气体中的锗浓度高，沉积温度较高）。利用表现出体积受限的传导特性（例如，氮化硅）的电介质层。除了硅锗合金的沉积之外，阵列加工是常规的。

68. 发明授权

US5030587A Method of forming substantially planar digit lines 失效
标题翻译：形成基本上平面的数字线的方法
公开(公告)号：US5030587A
公开(公告)日：1991-07-09
申请号：US534126
申请日：1990-06-05
申请人： Phillip G. Wald , Pierre Fazan
发明人： Phillip G. Wald , Pierre Fazan
IPC分类号： H01L21/768
CPC分类号： H01L21/768 , H01L21/76819 , H01L21/76885
摘要： A method of forming digit lines on a semiconductor wafer having integrated circuits comprises the following consecutive steps:selectively processing the wafer to produce a desired array of dynamic random access memory cells having associated word lines and exposed active areas, the word lines being defined by electrically conductive regions comprised of a polysilicon/high conductive material sandwich structure and having side and top electrically insulated regions comprised of oxide;providing a layer of doped epitaxial monocrystalline silicon atop exposed active areas to a height which is below the uppermost portions of the electrically insulated regions atop the word lines, and above the height of the uppermost portions of the word line electrically conductive regions;providing a layer of electrically insulating oxide atop the wafer, the electrically insulating layer having a lowest point which is higher than the height of the doped epitaxial silicon layer;planarizing the electrically insulating layer by removing electrically insulating material to provide a substantially planar upper layer of electrically insulating material at a height which is substantially coincident with a common height of the uppermost portions of the tops of the electrically insulated regions of the word lines;etching vias into the electrically insulating layer which generally align with doped epitaxial silicon;depositing an electrically conductive doped polysilicon layer atop the planarized and etched electrically insulating oxide layer; andetching the doped polysilicon layer to form desired substantially planar digit lines.
摘要翻译：在具有集成电路的半导体晶片上形成数字线的方法包括以下连续步骤：选择性地处理晶片以产生具有相关联的字线和暴露的有源区的期望阵列的动态随机存取存储器单元，字线由电导电区域由多晶硅/高导电材料夹层结构构成，并且具有由氧化物组成的侧面和顶部电绝缘区域; 在暴露的有源区域之上提供一层掺杂的外延单晶硅，该层高于在字线顶部的绝缘区域的最上部以及字线导电区域的最上部的高度以下的高度; 在所述晶片顶上提供一层电绝缘氧化物，所述电绝缘层的最低点高于所述掺杂的外延硅层的高度; 通过去除电绝缘材料来平坦化电绝缘层，以在与字线的电绝缘区域的顶部的最上部的公共高度基本一致的高度提供基本平坦的电绝缘材料上层; 将通孔蚀刻到通常与掺杂的外延硅对准的电绝缘层中; 在平坦化和蚀刻的电绝缘氧化物层的顶部沉积导电掺杂多晶硅层; 并蚀刻掺杂多晶硅层以形成所需的基本上平面的数字线。

69. 发明授权

US07732816B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07732816B2
公开(公告)日：2010-06-08
申请号：US11977705
申请日：2007-10-25
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： H01L29/04
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor integrated circuit device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.
摘要翻译：公开了一种半导体集成电路器件，例如存储器件或放射线检测器，其中数据存储单元形成在衬底上。每个数据存储单元包括具有源极，漏极和栅极的场效应晶体管，以及布置在源极和漏极之间的用于存储在体内产生的电荷的主体。体内净电荷的大小可以通过施加到晶体管的输入信号来调节，并且可以通过在栅极和漏极之间施加电压信号来至少部分地抵消由输入信号调节净电荷在源和漏之间。

70. 发明授权

US07239549B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07239549B2
公开(公告)日：2007-07-03
申请号：US11132979
申请日：2005-05-19
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C16/04
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.
摘要翻译：公开了诸如存储器件或辐射检测器的半导体器件，其中在衬底上形成数据存储单元。每个数据存储单元包括具有源极，漏极和栅极的场效应晶体管，以及布置在源极和漏极之间的用于存储在体内产生的电荷的主体。体内净电荷的大小可以通过施加到晶体管的输入信号来调节，并且可以通过在栅极和漏极之间施加电压信号来至少部分地抵消由输入信号调节净电荷在源和漏之间。

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