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61. 发明申请

US20120052662A1 METHOD FOR PURIFICATION OF SEMICONDUCTING SINGLE WALL NANOTUBES 有权
标题翻译：半导体单壁纳米管的纯化方法
公开(公告)号：US20120052662A1
公开(公告)日：2012-03-01
申请号：US13290648
申请日：2011-11-07
申请人： Eugene P. Marsh , Gurtej S. Sandhu
发明人： Eugene P. Marsh , Gurtej S. Sandhu
IPC分类号： H01L21/04 , H01B1/04 , B82B3/00 , B82Y40/00
CPC分类号： B82Y30/00 , B82Y40/00 , C01B32/17 , C01B2202/02 , C01B2202/06 , C01B2202/22 , C01B2202/34 , Y10T428/249924 , Y10T428/249953 , Y10T428/2918
摘要： A process of forming a semiconductive carbon nanotube structure includes imposing energy on a mixture that contains metallic carbon nanotubes and semiconductive carbon nanotubes under conditions to cause the metallic carbon nanotubes to be digested or to decompose so that they may be separated away from the semiconductive carbon nanotubes.
摘要翻译：形成半导体碳纳米管结构的方法包括在使金属碳纳米管被消化或分解的条件下在包含金属碳纳米管和半导体碳纳米管的混合物上施加能量，使得它们可以与半导体碳纳米管分离。

62. 发明申请

US20120051132A1 MEMORY CELL STRUCTURES AND METHODS 有权
公开(公告)号：US20120051132A1
公开(公告)日：2012-03-01
申请号：US12872368
申请日：2010-08-31
申请人： Gurtej S. Sandhu , Bhaskar Srinivasan
发明人： Gurtej S. Sandhu , Bhaskar Srinivasan
IPC分类号： G11C11/36 , G11C11/34
CPC分类号： G11C16/0416 , G11C16/0483
摘要： Memory cell structures and methods are described herein. One or more memory cells include a transistor having a charge storage node, a dielectric material positioned between the charge storage node and a channel region of the transistor, the channel region positioned between a source region and a drain region, and a first electrode of a diode coupled to the charge storage node.

63. 发明申请

US20120039790A1 Nanotube Separation Methods 有权
标题翻译：纳米管分离方法
公开(公告)号：US20120039790A1
公开(公告)日：2012-02-16
申请号：US13276150
申请日：2011-10-18
申请人： Gurtej S. Sandhu
发明人： Gurtej S. Sandhu
IPC分类号： D01F9/12 , B82Y40/00
CPC分类号： B01D21/262 , B01D43/00 , B82Y30/00 , B82Y40/00 , C01B32/172 , Y10S977/745 , Y10S977/746 , Y10S977/845 , Y10S977/847
摘要： A nanotube separation method includes depositing a tag on a nanotube in a nanotube mixture. The nanotube has a defect and the tag deposits at the defect where a deposition rate is greater than on another nanotube in the mixture lacking the defect. The method includes removing the tagged nanotube from the mixture by using the tag. As one option, the tag may contain a ferromagnetic material and the removing may include applying a magnetic field. As another option, the tag may contain an ionic material and the removing may include applying an electric field. As a further option, the tag may contain an atom having an atomic mass greater than the atomic mass of carbon and the removing may include applying a centrifugal force to the nanotube mixture. Any two or more of the indicated removal techniques may be combined.
摘要翻译：纳米管分离方法包括在纳米管混合物中的纳米管上沉积标签。纳米管具有缺陷，并且标记沉积在缺陷处，其中沉积速率大于缺少缺陷的混合物中的另一纳米管上的沉积速率。该方法包括通过使用标签从混合物中去除标记的纳米管。作为一种选择，标签可以包含铁磁材料，并且去除可以包括施加磁场。作为另一选择，标签可以包含离子材料，并且去除可以包括施加电场。作为另一选择，标签可以包含原子质量大于碳原子质量的原子，并且除去可包括向纳米管混合物施加离心力。可以组合指示的去除技术中的任何两种或更多种。

64. 发明申请

US20120006580A1 Electrically Conductive Laminate Structures, Electrical Interconnects, And Methods Of Forming Electrical Interconnects 有权
标题翻译：导电层压结构，电气互连和形成电气互连的方法
公开(公告)号：US20120006580A1
公开(公告)日：2012-01-12
申请号：US12833074
申请日：2010-07-09
申请人： Gurtej S. Sandhu
发明人： Gurtej S. Sandhu
IPC分类号： H01B5/00 , H05K13/00 , B05D5/12
CPC分类号： H01L23/53276 , H01L21/76805 , H01L21/76843 , H01L21/76847 , H01L21/76865 , H01L21/76877 , H01L23/53209 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene regions. In some embodiments the graphene and non-graphene regions may be nested within one another. In some embodiments an electrically insulative material may be over an upper surface of the laminate structure, and an opening may extend through the insulative material to a portion of the laminate structure. Electrically conductive material may be within the opening and in electrical contact with at least one of the non-graphene regions of the laminate structure. Some embodiments include methods of forming electrical interconnects in which non-graphene material and graphene are alternately formed within a trench to form nested non-graphene and graphene regions.
摘要翻译：一些实施例包括电互连。互连可以包含层压结构，其具有夹在非石墨烯区域之间的石墨烯区域。在一些实施例中，石墨烯和非石墨烯区域可以彼此嵌套。在一些实施例中，电绝缘材料可以在层压结构的上表面之上，并且开口可以延伸穿过绝缘材料到层压结构的一部分。导电材料可以在开口内并且与层压结构的非石墨烯区域中的至少一个电接触。一些实施例包括形成电互连的方法，其中在沟槽内交替形成非石墨烯材料和石墨烯以形成嵌套的非石墨烯和石墨烯区域。

65. 发明授权

US08093658B2 Electronic device with asymmetric gate strain 有权
标题翻译：具有不对称栅极应变的电子器件
公开(公告)号：US08093658B2
公开(公告)日：2012-01-10
申请号：US12697991
申请日：2010-02-01
申请人： Gurtej S. Sandhu , Kunal R. Parekh
发明人： Gurtej S. Sandhu , Kunal R. Parekh
IPC分类号： H01L29/76
CPC分类号： H01L29/4983 , H01L21/28114 , H01L21/823437 , H01L21/823456 , H01L21/823468 , H01L21/823807 , H01L21/823828 , H01L29/1033 , H01L29/1054 , H01L29/401 , H01L29/42376 , H01L29/6656 , H01L29/66659 , H01L29/7843 , H01L29/7845 , Y10S257/90
摘要： The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing structures as part of the gate electrode.
摘要翻译：在集成电路中使用应变栅电极导致晶体管具有改善的载流子迁移率，改进的驱动特性和减少的源极漏极结泄漏。栅电极应变可以通过不对称放置应力诱导结构作为栅电极的一部分获得。

66. 发明授权

US08084142B2 Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects 有权
标题翻译：向源极/漏极区形成导电接触的方法以及形成局部互连的方法
公开(公告)号：US08084142B2
公开(公告)日：2011-12-27
申请号：US11525762
申请日：2006-09-21
申请人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
发明人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
IPC分类号： H01L21/44 , H01L21/4763 , H01L29/40
CPC分类号： H01L21/76823 , H01L21/28512 , H01L21/76895 , Y10T428/12542
摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成对场效应晶体管的源极/漏极区的导电接触的方法，以及形成局部互连的方法。在一个实施方案中，形成到场效应晶体管的源/漏区的导电接触的方法包括在晶体管栅极和场效应晶体管的沟道区之间提供栅介质材料。至少一些栅极电介质材料延伸以在场效应晶体管的至少一个源极/漏极区域上接收。接收在一个源极/漏极区域上的栅极电介质材料暴露于有效地将其从电绝缘转变为导电并与一个源极/漏极区域导电接触的条件。考虑了其他方面和实现。

67. 发明授权

US08003542B2 Multiple spacer steps for pitch multiplication 有权
标题翻译：用于间距倍增的多个间隔步长
公开(公告)号：US08003542B2
公开(公告)日：2011-08-23
申请号：US12489337
申请日：2009-06-22
申请人： Sanket Sant , Gurtej S. Sandhu , Neal R. Rueger
发明人： Sanket Sant , Gurtej S. Sandhu , Neal R. Rueger
IPC分类号： H01L21/302
CPC分类号： H01L21/3088 , H01L21/0337 , H01L21/3085 , H01L21/3086 , H01L21/76802 , H01L27/1052
摘要： Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.
摘要翻译：使用多个间距倍数的间隔物来形成具有特别小的临界尺寸的特征的掩模图案。去除围绕多个心轴形成的每对间隔件中的一个，并且由两个相互选择性可蚀刻的材料形成的交替层围绕剩余的间隔物沉积。然后蚀刻由一种材料形成的层，留下由形成掩模图案的另一种材料形成的垂直延伸层。或者，代替沉积交替层，无定形碳沉积在剩余的间隔物周围，随后在无定形碳上形成一对间隔物的多个循环，去除一对隔离物中的一个并沉积无定形碳层。可以重复循环以形成所需的图案。由于图案中的某些特征的临界尺寸可以通过控制间隔物之间的间隔的宽度来设定，所以可以形成特别小的掩模特征。

68. 发明申请

US20110139368A1 APPARATUS AND SYSTEMS FOR INTEGRATED CIRCUIT DIAGNOSIS 审中-公开
标题翻译：集成电路诊断的装置和系统
公开(公告)号：US20110139368A1
公开(公告)日：2011-06-16
申请号：US13031022
申请日：2011-02-18
申请人： Mark J. Williamson , Gurtej S. Sandhu , Justin R. Arrington
发明人： Mark J. Williamson , Gurtej S. Sandhu , Justin R. Arrington
IPC分类号： H01L21/306
CPC分类号： H01L22/14 , G01R31/2898 , H01J37/252 , H01J37/28 , H01J37/3056 , H01J2237/24564 , H01J2237/24592
摘要： Apparatus and systems provide a mechanism to examine physical properties and/or diagnose problems at a selected location of an integrated circuit. Such apparatus and systems can include a source of an energetic beam directed at the selected location. The apparatus and systems may be used to provide examination and/or diagnostic methods that may be used in areas smaller than one micron in diameter and that may be used to remove IC layers, either selectively or non-selectively, until a desired depth is obtained.
摘要翻译：装置和系统提供了一种检查在集成电路的选定位置处的物理特性和/或诊断问题的机制。这样的装置和系统可以包括指向所选位置的能量束的源。该装置和系统可用于提供可用于直径小于1微米的区域的检查和/或诊断方法，并且可用于选择性地或非选择性地去除IC层，直到获得期望的深度。

69. 发明授权

US07923308B2 Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects 有权
公开(公告)号：US07923308B2
公开(公告)日：2011-04-12
申请号：US11478715
申请日：2006-06-30
申请人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
发明人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
IPC分类号： H01L21/332 , H01L21/336 , H01L21/4763
CPC分类号： H01L21/76823 , H01L21/28512 , H01L21/76895 , Y10T428/12542
摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.

70. 发明申请

US20100267240A1 PITCH MULTIPLICATION SPACERS AND METHODS OF FORMING THE SAME 有权
公开(公告)号：US20100267240A1
公开(公告)日：2010-10-21
申请号：US12827506
申请日：2010-06-30
申请人： Gurtej S. Sandhu , Kirk D. Prall
发明人： Gurtej S. Sandhu , Kirk D. Prall
IPC分类号： H01L21/302 , C23F1/08
CPC分类号： H01L21/67063 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/32053 , H01L21/32134
摘要： Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate.
摘要翻译：在不执行间隔物蚀刻的情况下形成间距倍增过程中的间隔物。相反，心轴形成在衬底上，然后心轴的侧面例如在氧化，氮化或硅化步骤中反应，以形成相对于心轴的未反应部分可以选择性去除的材料。选择性地去除未反应部分以留下独立间隔物的图案。独立的间隔物可以用作后续处理步骤的掩模，例如蚀刻基底。

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