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61. 发明授权

US07538653B2 Grounding of magnetic cores 有权
标题翻译：磁芯接地
公开(公告)号：US07538653B2
公开(公告)日：2009-05-26
申请号：US11694812
申请日：2007-03-30
申请人： Gerhard Schrom , Donald Gardner , Peter Hazucha , Fabrice Paillet , Tanay Karnik
发明人： Gerhard Schrom , Donald Gardner , Peter Hazucha , Fabrice Paillet , Tanay Karnik
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F3/00 , H01F27/34 , H01F2017/0066
摘要： An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
摘要翻译：一种装置包括磁芯，接地节点和一个或多个通孔，以提供磁芯和地电位之间的连接。磁芯包括第一磁性层和第二磁性层。另外，该装置可以包括导电图案。导电图案可以在第一和第二磁性层之间的第三层。该装置可以包括在使用铁磁芯或屏蔽的电感器，变压器，传输线和其它部件中。这样的部件可以集成在芯片或芯片上。

62. 发明授权

US07504808B2 Multiphase transformer for a multiphase DC-DC converter 有权
标题翻译：多相DC-DC转换器的多相变压器
公开(公告)号：US07504808B2
公开(公告)日：2009-03-17
申请号：US11173065
申请日：2005-06-30
申请人： Gerhard Schrom , Peter Hazucha , Jaeseo Lee , Fabrice Paillet , Tanay Karnik , Vivek De
发明人： Gerhard Schrom , Peter Hazucha , Jaeseo Lee , Fabrice Paillet , Tanay Karnik , Vivek De
IPC分类号： G05F1/00
CPC分类号： G05F1/468 , H02M1/14 , H02M7/068
摘要： A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.
摘要翻译：提供了一种包括多相变压器的多相DC-DC转换器，多相变压器包括多个输入电压端子和变压器输出电压端子，每个输入电压端子与相应的相位相关联。将各相分配给多个输入电压端子的输入电压端子，以使多相变压器的输入电压端子处的纹波电流最小化。

63. 发明授权

US07372382B2 Voltage regulation using digital voltage control 有权
标题翻译：电压调节采用数字电压控制
公开(公告)号：US07372382B2
公开(公告)日：2008-05-13
申请号：US11167978
申请日：2005-06-27
申请人： Peter Hazucha , Saravanan Rajapandian , Gerhard Schrom , Tanay Karnik , Vivek De
发明人： Peter Hazucha , Saravanan Rajapandian , Gerhard Schrom , Tanay Karnik , Vivek De
IPC分类号： H03M1/00
CPC分类号： G05F1/56
摘要： For one disclosed embodiment, error is sensed in a voltage at an output node. One or more analog signals are generated based on the sensed error. One or more generated analog signals are converted into one or more digital signals. The voltage at the output node is controlled in response to the one or more digital signals.
摘要翻译：对于一个公开的实施例，在输出节点处的电压中感测到误差。基于感测到的误差产生一个或多个模拟信号。一个或多个产生的模拟信号被转换成一个或多个数字信号。响应于一个或多个数字信号来控制输出节点处的电压。

64. 发明申请

US20070260848A1 Power mangement integrated circuit 有权
标题翻译：电力管理集成电路
公开(公告)号：US20070260848A1
公开(公告)日：2007-11-08
申请号：US11825252
申请日：2007-07-03
申请人： Siva Narendra , James Tschanz , Howard Wilson , Donald Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek De , Shekhar Borkar
发明人： Siva Narendra , James Tschanz , Howard Wilson , Donald Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek De , Shekhar Borkar
IPC分类号： G06F15/00 , H01L21/50 , H01L23/34
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。

65. 发明申请

US20070001762A1 DC-DC converter switching transistor current measurement technique 有权
标题翻译： DC-DC转换器开关晶体管电流测量技术
公开(公告)号：US20070001762A1
公开(公告)日：2007-01-04
申请号：US11173760
申请日：2005-06-30
申请人： Gerhard Schrom , Peter Hazucha , Vivek De , Tanay Karnik
发明人： Gerhard Schrom , Peter Hazucha , Vivek De , Tanay Karnik
IPC分类号： H03F3/45
CPC分类号： H02M3/155 , G01R19/0092 , H02M2001/0009
摘要： A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor's conductive channel. The second current is less than and proportional to the first current.
摘要翻译：描述了一种方法，其包括通过开关晶体管导通第一电流。该方法还包括通过一对晶体管导通第二电流，导体沟道相对于彼此串联耦合并且一起并联耦合在开关晶体管的导电沟道上。第二电流小于并与第一电流成比例。

66. 发明申请

US20060273872A1 Power transformer 有权
标题翻译：电力变压器
公开(公告)号：US20060273872A1
公开(公告)日：2006-12-07
申请号：US11141320
申请日：2005-06-01
申请人： Peter Hazucha , Gerhard Schrom , Weimin Shi , Edward Burton , Trang Nguyen , Bradley Bloechel , Mary Bloechel , Tanay Karnik
发明人： Peter Hazucha , Gerhard Schrom , Weimin Shi , Edward Burton , Trang Nguyen , Bradley Bloechel , Mary Bloechel , Tanay Karnik
IPC分类号： H01F30/12
CPC分类号： H01F27/2804 , H01F17/0013 , H01F30/06 , H01F30/12 , H01F2038/006
摘要： A multi-phase transformer is provided that includes a first layer having at least a first planar wire and a second planar wire and a second layer formed on the first layer and having at least a third planar wire and a fourth planar wires. At least the first planar wire and the second planar wire of the first layer to form two transformers with at least two planar wires of the second layer. The multi-phase transformer may also include a coupling device to couple one end of the planar wires of the first layer with one of the planar wires of the second layer.
摘要翻译：提供一种多相变压器，其包括具有至少第一平面线和第二平面线的第一层和形成在第一层上并具有至少第三平面线和第四平面线的第二层的第一层。至少第一层的第一平面线和第二平面线，以形成具有第二层的至少两个平面线的两个变压器。多相变压器还可以包括将第一层的平面线的一端与第二层的平面线之一耦合的耦合装置。

67. 发明申请

US20060224337A1 Programmable current load systems and methods 审中-公开
标题翻译：可编程电流负载系统和方法
公开(公告)号：US20060224337A1
公开(公告)日：2006-10-05
申请号：US11095950
申请日：2005-03-31
申请人： Peter Hazucha , Gerhard Schrom , Tanay Karnik
发明人： Peter Hazucha , Gerhard Schrom , Tanay Karnik
IPC分类号： G01R19/00
CPC分类号： G06F1/28
摘要： One disclosed system includes a plurality of current sink elements coupled between a power supply and a reference potential. A plurality of multiplexers are configured to enable the current sink elements to sink current, and a plurality of selection inputs are configured to control the state of the multiplexers.
摘要翻译：一个公开的系统包括耦合在电源和参考电位之间的多个电流吸收元件。多个多路复用器被配置为使得当前宿元件能够吸收电流，并且多个选择输入被配置为控制多路复用器的状态。

68. 发明申请

US20060099734A1 CPU power delivery system 有权
标题翻译： CPU供电系统
公开(公告)号：US20060099734A1
公开(公告)日：2006-05-11
申请号：US10955746
申请日：2004-09-30
申请人： Siva Narendra , Howard Wilson , Donald Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek De , Shekhar Borkar
发明人： Siva Narendra , Howard Wilson , Donald Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek De , Shekhar Borkar
IPC分类号： H01L21/50
CPC分类号： H01L25/18 , G06F1/189 , G06F1/26 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2924/00011 , H01L2924/00014 , H01L2924/3011 , H01L2224/0401
摘要： A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种中央处理单元（CPU）。 CPU包括CPU管芯; 以及以三维封装布局结合到CPU裸片的电压调节器芯片。

69. 发明申请

US20050140415A1 Timing circuit for separate positive and negative edge placement in a switching DC-DC converter 失效
标题翻译：用于在开关DC-DC转换器中单独的正和负边缘放置的定时电路
公开(公告)号：US20050140415A1
公开(公告)日：2005-06-30
申请号：US10748298
申请日：2003-12-31
申请人： Peter Hazucha , Gerhard Schrom , Tanay Karnik , Vivek De
发明人： Peter Hazucha , Gerhard Schrom , Tanay Karnik , Vivek De
IPC分类号： H02M3/157 , H03H11/26 , H03K5/135
CPC分类号： H03K5/135 , H02M3/157
摘要： A timing circuit independently controls placement of the positive and negative edges of a periodic signal. This signal may then be used to control a wide variety of integrated circuit applications. The timing circuit includes separate programmable delay lines and a signal processor. Each delay line delays an input clock signal by a different increment of time. The signal processor then generates a timing signal from the clock signal, where the timing signal has a first edge controlled by the first delayed clock signal and a second edge controlled by the second delayed clock signal. The edges may be controlled so that the timing signal assumes different logical values for different amounts of time, thereby customizing the signal to any application. An example of one application includes using the timing signal control switching in a DC-DC converter.
摘要翻译：定时电路独立地控制周期信号的正和负边缘的放置。然后可以将该信号用于控制各种各样的集成电路应用。定时电路包括单独的可编程延迟线和信号处理器。每个延迟线将输入时钟信号延迟不同的时间增量。信号处理器随后从时钟信号产生定时信号，其中定时信号具有由第一延迟时钟信号控制的第一边沿和由第二延迟时钟信号控制的第二边沿。可以控制边缘使得定时信号在不同的时间量内采用不同的逻辑值，从而将信号定制到任何应用。一个应用的示例包括在DC-DC转换器中使用定时信号控制切换。

70. 发明授权

US08361594B2 Methods of forming magnetic vias to maximize inductance in integrated circuits and structures formed thereby 有权
标题翻译：形成磁通孔的方法，以使集成电路中的电感和由此形成的结构最大化
公开(公告)号：US08361594B2
公开(公告)日：2013-01-29
申请号：US11936724
申请日：2007-11-07
申请人： Donald Gardner , Gerhard Schrom , Peter Hazucha , Fabrice Paillet , Tanay Karnik
发明人： Donald Gardner , Gerhard Schrom , Peter Hazucha , Fabrice Paillet , Tanay Karnik
IPC分类号： B32B3/24 , H01F7/06 , H01F5/00
CPC分类号： H01F41/046 , H01F17/0006 , H01F27/324 , H01F2017/0066 , H01L23/5227 , H01L2924/0002 , Y10T29/4902 , Y10T428/24331 , H01L2924/00
摘要： Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of a magnetic material on a substrate, forming an oxide layer on the first layer of the magnetic material, forming at least one conductive structure on the first magnetic layer, forming a dielectric layer on the at least one conductive structure, forming a second layer of the magnetic material on the at least one conductive structure, and forming a magnetic via coupled to the first and second layers of the magnetic material, wherein the magnetic via comprises a shape to increase inductance of the inductive structure.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法可以包括在衬底上形成磁性材料的第一层，在磁性材料的第一层上形成氧化物层，在第一磁性层上形成至少一个导电结构，在至少一个上形成介电层在所述至少一个导电结构上形成所述磁性材料的第二层，以及形成耦合到所述磁性材料的所述第一和第二层的磁通孔，其中所述磁通孔包括增加所述电感结构的电感的形状。

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