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61. 发明申请

US20140277812A1 DUAL LOOP DIGITAL LOW DROP REGULATOR AND CURRENT SHARING CONTROL APPARATUS FOR DISTRIBUTABLE VOLTAGE REGULATORS 审中-公开
标题翻译：双环数字低电平调节器和分布式电压调节器的电流共享控制装置
公开(公告)号：US20140277812A1
公开(公告)日：2014-09-18
申请号：US13801777
申请日：2013-03-13
申请人： Yi-Chun Shih , Kaushik Mazumdar , Stephen T. Kim , Rinkle Jain , James W. Tschanz , Muhammad M. Khellah
发明人： Yi-Chun Shih , Kaushik Mazumdar , Stephen T. Kim , Rinkle Jain , James W. Tschanz , Muhammad M. Khellah
IPC分类号： G05F5/00
CPC分类号： G05F1/563 , G05F1/00 , G05F1/46 , H02M3/156
摘要： Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.
摘要翻译：描述了一种装置，其包括：耦合到输入电源和负载的多个晶体管; 第一比较器，其具有耦合到所述负载的第一节点，以及耦合到第一参考的第二节点; 第二比较器，其具有耦合到所述负载的第一节点，以及耦合到第二参考的第二节点，所述第二参考与所述第一参考不同; 以及逻辑单元，用于接收第一比较器的输出和第二比较器的输出，逻辑单元根据第一和第二比较器的输出接通或关断多个晶体管的晶体管。

62. 发明授权

US08762821B2 Method of correcting adjacent errors by using BCH-based error correction coding 有权
标题翻译：通过使用基于BCH的纠错编码校正相邻误差的方法
公开(公告)号：US08762821B2
公开(公告)日：2014-06-24
申请号：US13435152
申请日：2012-03-30
申请人： Wei Wu , Shih-Lien L. Lu , Muhammad M. Khellah
发明人： Wei Wu , Shih-Lien L. Lu , Muhammad M. Khellah
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F11/1064 , H03M13/152 , H03M13/1575
摘要： An apparatus is provided that comprises a processor. The processor comprises a cache to store data, a decoder, an error classification module, and an error correction module. The cache stores data, the data encoded as a codeword. The decoder reads the codeword from cache and calculates a syndrome of the codeword using an H-matrix. The error classification module determines an error type of the syndrome. The H-matrix is redesigned such that the columns form a geometrical sequence, and as a result not only t-bit random errors but also (t+1) bit adjacent errors can be corrected. The error correction module, triggered by the enhanced error classification module, takes one of two sets of inputs depending on error type (either random error or adjacent error) and produces corrected data from the syndrome when the syndrome comprises a detectable and correctable error.
摘要翻译：提供了一种包括处理器的装置。处理器包括用于存储数据的缓存，解码器，错误分类模块和纠错模块。高速缓存存储数据，数据被编码为码字。解码器从缓存器读取码字，并使用H矩阵计算码字的校正子。错误分类模块确定综合征的错误类型。 H矩阵被重新设计，使得列形成几何序列，结果不仅可以校正t位随机误差，而且可以校正（t + 1）位相邻误差。由增强的误差分类模块触发的误差校正模块根据误差类型（随机误差或相邻误差）采用两组输入中的一组，并且当综合征包括可检测和可校正的误差时，产生校正数据。

63. 发明申请

US20140003181A1 MEMORY CELL WITH IMPROVED WRITE MARGIN 有权
标题翻译：具有改进的写字符的存储单元
公开(公告)号：US20140003181A1
公开(公告)日：2014-01-02
申请号：US13997633
申请日：2012-03-30
申请人： Yih Wang , Muhammad M. Khellah , Fatih Hamzaoglu
发明人： Yih Wang , Muhammad M. Khellah , Fatih Hamzaoglu
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/14 , G11C5/147 , G11C5/148 , G11C11/4074 , G11C11/412 , G11C11/413 , G11C11/417
摘要： Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.
摘要翻译：描述了一种用于改善存储器单元中的写入裕度的装置和系统。在一个实施例中，该装置包括：提供具有宽度的脉冲信号的第一电路; 以及第二电路，用于接收所述脉冲信号并产生用于所述存储器单元的电源，其中所述第二电路将所述电源的电平降低到所述存储单元的数据保持电压电平以下一段对应于所述宽度的时间段的脉冲信号。在一个实施例中，该装置包括具有高供应节点和低供应节点的一列存储器单元; 以及位于存储单元列中的电荷共享电路，所述电荷共享电路耦合到所述高电源节点和所述低电源节点，所述电荷共享电路可操作以减少直流（DC）功率消耗。

64. 发明申请

US20130262957A1 Method Of Correcting Adjacent Errors By Using BCH-Based Error Correction Coding 有权
标题翻译：通过使用基于BCH的纠错编码校正相邻错误的方法
公开(公告)号：US20130262957A1
公开(公告)日：2013-10-03
申请号：US13435152
申请日：2012-03-30
申请人： Wei Wu , Shih-Lien L. Lu , Muhammad M. Khellah
发明人： Wei Wu , Shih-Lien L. Lu , Muhammad M. Khellah
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： G06F11/1064 , H03M13/152 , H03M13/1575
摘要： An apparatus is provided that comprises a processor. The processor comprises a cache to store data, a decoder, an error classification module, and an error correction module. The cache stores data, the data encoded as a codeword. The decoder reads the codeword from cache and calculates a syndrome of the codeword using an H-matrix. The error classification module determines an error type of the syndrome. The H-matrix is redesigned such that the columns form a geometrical sequence, and as a result not only the t-bit random errors but also (t+1) bit adjacent errors can be corrected. The error correction module, triggered by the enhanced error classification module, takes one of two sets of inputs depends on the error type (either random or adjacent error) and produces corrected data from the syndrome when the syndrome comprises a detectable and correctable error.
摘要翻译：提供了一种包括处理器的装置。处理器包括用于存储数据的缓存，解码器，错误分类模块和纠错模块。高速缓存存储数据，数据被编码为码字。解码器从缓存器读取码字，并使用H矩阵计算码字的校正子。错误分类模块确定综合征的错误类型。 H矩阵被重新设计，使得列形成几何序列，结果不仅可以校正t位随机误差，而且（t + 1）位相邻误差。由增强的误差分类模块触发的误差校正模块根据误差类型（随机或相邻误差）采用两组输入中的一组，并且当综合征包括可检测和可校正的误差时，产生校正数据。

65. 发明授权

US09665144B2 Methods and systems for energy efficiency and energy conservation including entry and exit latency reduction for low power states 有权
公开(公告)号：US09665144B2
公开(公告)日：2017-05-30
申请号：US13333753
申请日：2011-12-21
申请人： Jawad Nasrullah , Kelvin Kwan , Jaydeep P. Kulkarni , Muhammad M. Khellah
发明人： Jawad Nasrullah , Kelvin Kwan , Jaydeep P. Kulkarni , Muhammad M. Khellah
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： Systems and methods for entry and exit latency reduction for low power states are described. In one embodiment, a computer implemented method initiates an energy-efficient low power state (e.g., deep sleep state) to reduce power consumption of a device. The method sets a power supply voltage that provides sufficient power to a dual power supply array for retention of states. Logic is powered down in this low power state.

66. 发明申请

US20150177823A1 GRAPHICS PROCESSOR SUB-DOMAIN VOLTAGE REGULATION 有权
标题翻译：图形处理器子域电压调节
公开(公告)号：US20150177823A1
公开(公告)日：2015-06-25
申请号：US14134598
申请日：2013-12-19
申请人： Subramaniam Maiyuran , Muhammad M. Khellah , James W. Tschanz
发明人： Subramaniam Maiyuran , Muhammad M. Khellah , James W. Tschanz
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/324 , G06F1/3243 , G06F1/3287 , Y02D10/126 , Y02D10/152 , Y02D10/171 , Y02D10/172
摘要： Voltage regulation of processor sub-domains supplied by a same voltage domain power supply rail. Voltage to certain logic units within the voltage domain may be reduced relative to other logic units of the voltage domain, reducing idle time at high power. In an embodiment, a first voltage-regulated sub-domain includes at least one execution unit (EU) while a second voltage-regulated sub-domain includes at least one texture sampler to provide flexibility in setting the graphics core power-performance point beyond modulating active EU count through power domain (gating) control. In embodiments, a sub-domain voltage is regulated by an on-chip DLDO for fast voltage switching. Clock frequency and sub-domain voltage may be switched faster than the voltage of the voltage domain supply rail, permitting a more finely grained power management that can be responsive to EU workload demand.
摘要翻译：由相同的电压域电源轨提供的处理器子域的电压调节。电压域内的某些逻辑单元的电压可以相对于电压域的其它逻辑单元减小，从而在高功率下减少空闲时间。在一个实施例中，第一电压调节子域包括至少一个执行单元（EU），而第二电压调节子域包括至少一个纹理采样器，以提供设置图形核心功率性能点超出调制的灵活性通过电源域（门控）控制有效的欧盟计数。在实施例中，子域电压由用于快速电压切换的片上DLDO调节。时钟频率和子域电压可能比电压域电源轨的电压更快，从而允许更精细的电源管理，可以响应欧盟的工作负载需求。

67. 发明授权

US08103830B2 Disabling cache portions during low voltage operations 有权
标题翻译：在低电压操作期间禁用缓存部分
公开(公告)号：US08103830B2
公开(公告)日：2012-01-24
申请号：US12242321
申请日：2008-09-30
申请人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/16
CPC分类号： G06F12/0895 , G06F1/3203 , G06F1/3275 , G06F1/3296 , G06F12/0864 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
摘要翻译：描述了在低电压操作期间禁用一个或多个高速缓存部分的方法和装置。在一些实施例中，一个或多个额外的比特可以用于高速缓存的一部分，其指示高速缓存的部分是否能够在Vccmin等级或更低的值下运行。还描述和要求保护其他实施例。

68. 发明申请

US20100082905A1 DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS 有权
标题翻译：在低电压运行期间禁用高速缓存部分
公开(公告)号：US20100082905A1
公开(公告)日：2010-04-01
申请号：US12242321
申请日：2008-09-30
申请人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F1/3203 , G06F1/3275 , G06F1/3296 , G06F12/0864 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
摘要翻译：描述了在低电压操作期间禁用一个或多个高速缓存部分的方法和装置。在一些实施例中，一个或多个额外的比特可以用于高速缓存的一部分，其指示高速缓存的部分是否能够在Vccmin等级或更低的值下运行。还描述和要求保护其他实施例。

69. 发明授权

US08868836B2 Reducing minimum operating voltage through hybrid cache design 有权
标题翻译：通过混合缓存设计降低最低工作电压
公开(公告)号：US08868836B2
公开(公告)日：2014-10-21
申请号：US12006287
申请日：2007-12-31
申请人： Muhammad M. Khellah , Christopher Wilkerson , Alaa R. Alameldeen , Bibiche M. Geuskens , Tanay Karnik , Vivek De , Gunjan H. Pandya
发明人： Muhammad M. Khellah , Christopher Wilkerson , Alaa R. Alameldeen , Bibiche M. Geuskens , Tanay Karnik , Vivek De , Gunjan H. Pandya
IPC分类号： G06F12/00
CPC分类号： G11C5/14 , G06F12/0802 , G06F2212/1028 , G11C11/412 , G11C11/413 , Y02D10/13
摘要： Methods and apparatus to reduce minimum operating voltage through a hybrid cache design are described. In one embodiment, a cache with different size bit cells may be used, e.g., to reduce minimum operating voltage of an integrated circuit device that includes the cache and possibly other logic (such as a processor). Other embodiments are also described.
摘要翻译：描述了通过混合高速缓存设计降低最小工作电压的方法和装置。在一个实施例中，可以使用具有不同大小的位单元的高速缓存，例如以减少包括高速缓存和可能的其它逻辑（例如处理器）的集成电路设备的最小工作电压。还描述了其它实施例。

70. 发明授权

US08291168B2 Disabling cache portions during low voltage operations 失效
公开(公告)号：US08291168B2
公开(公告)日：2012-10-16
申请号：US13342016
申请日：2011-12-31
申请人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/16
CPC分类号： G06F12/0895 , G06F1/3203 , G06F1/3275 , G06F1/3296 , G06F12/0864 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

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