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61. 发明申请

US20100214821A1 CAPACITIVE DIVIDER SENSING OF MEMORY CELLS 有权
标题翻译：记忆细胞的电容分辨率检测
公开(公告)号：US20100214821A1
公开(公告)日：2010-08-26
申请号：US12770362
申请日：2010-04-29
申请人： Jennifer E. Taylor , John D. Porter
发明人： Jennifer E. Taylor , John D. Porter
IPC分类号： G11C11/00 , G11C7/06 , G11C5/14
CPC分类号： G11C13/004 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2013/0054 , G11C2211/5634
摘要： The present disclosure includes devices and methods for sensing resistance variable memory cells. One device embodiment includes at least one resistance variable memory cell, and a capacitive divider configured to generate multiple reference levels in association with the at least one resistance variable memory cell.
摘要翻译：本公开包括用于感测电阻可变存储单元的装置和方法。一个器件实施例包括至少一个电阻可变存储器单元和电容分压器，其被配置成与至少一个电阻变量存储单元相关联地产生多个参考电平。

62. 发明申请

US20090244961A1 PHASE CHANGE MEMORY 有权
标题翻译：相变记忆
公开(公告)号：US20090244961A1
公开(公告)日：2009-10-01
申请号：US12056045
申请日：2008-03-26
申请人： Pradeep Ramani , John D. Porter
发明人： Pradeep Ramani , John D. Porter
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： The present disclosure includes devices and methods for operating phase change memory cells. One or more embodiments include applying a programming signal to a phase change material of a memory cell, and decreasing a magnitude of a trailing portion of the applied programming signal successively according to a number of particular decrements. The magnitude and the duration of the number of particular decrements correspond to particular programmed values.
摘要翻译：本公开包括用于操作相变存储器单元的装置和方法。一个或多个实施例包括将编程信号施加到存储器单元的相变材料，以及根据特定减量的数量连续减小所应用的编程信号的尾部的幅度。特定减量数量的大小和持续时间对应于特定的编程值。

63. 发明授权

US07405463B2 Gate dielectric antifuse circuit to protect a high-voltage transistor 有权
标题翻译：栅介质反熔丝电路保护高压晶体管
公开(公告)号：US07405463B2
公开(公告)日：2008-07-29
申请号：US11426523
申请日：2006-06-26
申请人： Kenneth W. Marr , John D. Porter
发明人： Kenneth W. Marr , John D. Porter
IPC分类号： H01L29/04 , H01L29/10 , H01L31/036
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/0248 , H01L29/0847 , H01L29/1045 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.
摘要翻译：根据本发明的实施例，电路具有用于保护栅介质反熔丝电路中的高压晶体管的元件。反熔丝在耦合以接收升高电压的第一端子和第二端子之间具有栅极电介质层，并且高压晶体管耦合到反熔丝并具有栅极端子。电源电压和升高电压之间的中间电压耦合到高电压晶体管的栅极端子，以保护高压晶体管。

64. 发明授权

US07126871B2 Circuits and methods to protect a gate dielectric antifuse 有权
标题翻译：保护栅极电介质反熔丝的电路和方法
公开(公告)号：US07126871B2
公开(公告)日：2006-10-24
申请号：US10770800
申请日：2004-02-03
申请人： Kenneth W. Marr , John D. Porter
发明人： Kenneth W. Marr , John D. Porter
IPC分类号： G11C7/00
CPC分类号： G11C17/18 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： According to embodiments of the present invention, an antifuse circuit is operated by coupling an elevated voltage to a first terminal of an antifuse, controlling current in the antifuse with a program driver circuit coupled to a second terminal of the antifuse, and shunting current around the antifuse with a bypass circuit coupled between the first terminal of the antifuse and the program driver circuit to protect the antifuse. The antifuse includes a layer of gate dielectric between the first terminal and the second terminal. The embodiments of the present invention protect a gate dielectric antifuse.
摘要翻译：根据本发明的实施例，通过将提升的电压耦合到反熔丝的第一端子来操作反熔丝电路，通过耦合到反熔丝的第二端子的编程驱动器电路来控制反熔丝中的电流，反熔丝与耦合在反熔丝的第一端子和程序驱动电路之间的旁路电路以保护反熔丝。反熔丝包括在第一端子和第二端子之间的栅极电介质层。本发明的实施例保护栅极绝缘反熔丝。

65. 发明授权

US06949948B2 Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges 有权
标题翻译：数字逻辑器件具有极度偏斜的跳变点和复位电路，用于快速传播信号边沿
公开(公告)号：US06949948B2
公开(公告)日：2005-09-27
申请号：US10336503
申请日：2003-01-03
申请人： John D. Porter , Dean D. Gans , Larren G. Weber
发明人： John D. Porter , Dean D. Gans , Larren G. Weber
IPC分类号： H03K19/017 , H03K19/0175
CPC分类号： H03K19/01721
摘要： The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.
摘要翻译：本发明包括具有非常偏斜的跳变点的数字逻辑器件和用于快速传播信号边缘的复位电路。根据本发明的偏斜逻辑器件的实施例包括用于快速传播输入信号的所选择的“快速”边沿的反相器，缓冲器，或非门和“与非”门。另外的实施例包括脉冲展开器，存储器件，衬底，计算机系统和结合本发明的倾斜逻辑器件的方法。本发明的倾斜逻辑器件的每个实施例被配置为以与多米诺逻辑的速率相当的速率传播输出信号的快速上升沿或快速下降沿，即“快速”边沿。与传统CMOS逻辑器件相比，本发明的偏斜逻辑器件的优点是快速的边沿传播。此外，实际上所有的输入门加载都用于传播的快速边缘。此外，如本文所公开的复位网络由至少两个门缓冲，从而减少由倾斜逻辑器件的输入或输出所看到的负载。

66. 发明授权

US06445259B1 Method to find a value within a range using weighted subranges 有权
公开(公告)号：US06445259B1
公开(公告)日：2002-09-03
申请号：US09929605
申请日：2001-08-14
申请人： William N. Thompson , John D. Porter , Larren Gene Weber
发明人： William N. Thompson , John D. Porter , Larren Gene Weber
IPC分类号： H03H1130
CPC分类号： G11C7/1051 , G11C7/1069 , H03H7/40 , H03H11/245 , H03H11/28 , H03H17/0263
摘要： A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.

67. 发明授权

US06376297B1 Latch-up prevention for memory cells 失效
标题翻译：记忆细胞的锁定预防
公开(公告)号：US06376297B1
公开(公告)日：2002-04-23
申请号：US09368710
申请日：1999-08-05
申请人： John D. Porter , William N. Thompson
发明人： John D. Porter , William N. Thompson
IPC分类号： H01L218234
CPC分类号： H01L27/1104 , G11C11/412
摘要： An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCC through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.
摘要翻译：提供具有一对交叉耦合CMOS反相器的SRAM存储单元。形成每个CMOS反相器的上拉晶体管的源极通过其中形成各自的衬底的寄生电阻耦合到VCC。因此，p型上拉晶体管的源极总是处于小于或等于N阱的电位的电位，使得寄生PNP晶体管的发射极 - 基极结不能变为正向偏置，并且闭锁不能发生。

68. 发明授权

US06317381B1 Method and system for adaptively adjusting control signal timing in a memory device 有权
标题翻译：用于自适应地调整存储器件中的控制信号定时的方法和系统
公开(公告)号：US06317381B1
公开(公告)日：2001-11-13
申请号：US09457429
申请日：1999-12-07
申请人： Dean Gans , John R. Wilford , John D. Porter
发明人： Dean Gans , John R. Wilford , John D. Porter
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/22 , G11C8/18
摘要： A method and apparatus is described for selectively adjusting control signal timing in a memory device as a function of the frequency of an externally applied clock signal. The memory device includes clock sensing circuitry that receives the clock signal and responsively produces a plurality of speed signals that transition a plurality of times corresponding in number to the frequency of the clock signal. The memory device also includes a control signal delay circuit that receives a memory command signal and the speed signals, and responsively produces a delayed control signal having a time delay from the command signal corresponding to the number of transitions of the speed signal value. Significantly, the control signal is generated during a period of the clock signal that immediately follows a period of the clock signal when the delay of the control signal delay circuit is set.
摘要翻译：描述了用于根据外部施加的时钟信号的频率来选择性地调整存储器件中的控制信号定时的方法和装置。存储器件包括时钟感测电路，其接收时钟信号并且响应地产生多个速度信号，该速度信号在数量上对应于时钟信号的频率。存储装置还包括控制信号延迟电路，其接收存储器命令信号和速度信号，并响应于从与速度信号值的转换次数相对应的命令信号产生具有时间延迟的延迟控制信号。重要的是，当控制信号延迟电路的延迟被设置时，在紧接着时钟信号的周期的时钟信号的周期期间产生控制信号。

69. 发明授权

US06310820B1 Relaxed write timing for a memory device 有权
标题翻译：轻松的记忆设备的写时序
公开(公告)号：US06310820B1
公开(公告)日：2001-10-30
申请号：US09335195
申请日：1999-06-17
申请人： John D. Porter , William N. Thompson , Larren G. Weber
发明人： John D. Porter , William N. Thompson , Larren G. Weber
IPC分类号： G11C800
CPC分类号： G11C7/22
摘要： A memory device provides a relaxed write timing scheme that improves access time. The address and/or the data is set up to the memory array during a previous write cycle so that the next write cycle can proceed without delays produced in delivering the address and/or the data to the array during the write cycle in which the data is to be written to the array.
摘要翻译：存储器件提供了一种改善访问时间的轻松的写时序方案。地址和/或数据在先前写入周期期间被设置到存储器阵列，使得下一个写入周期可以在写入周期期间在数据传送期间产生延迟而进行，其中数据将被写入阵列。

70. 发明授权

US06239618B1 Buffer with fast edge propagation 有权
标题翻译：具有快速边缘传播的缓冲区
公开(公告)号：US06239618B1
公开(公告)日：2001-05-29
申请号：US09520057
申请日：2000-03-07
申请人： John D. Porter , Larren G. Weber , William N. Thompson
发明人： John D. Porter , Larren G. Weber , William N. Thompson
IPC分类号： H03K190175
CPC分类号： H03K5/023 , H03K5/12 , H03K5/1252
摘要： A buffer having first and second input terminals and an output terminal. The buffer also includes a fast edge driver having an input terminal and an output terminal, with the input terminal connected to the first input terminal of the buffer, and the output terminal connected to the output terminal of the buffer. A shielding circuit is provided having an input terminal and an output terminal, with the input terminal connected to the second input terminal of the buffer. The buffer further includes a recovery circuit having an input terminal and an output terminal, with the input terminal connected to the output terminal of the shielding circuit, and the output terminal connected to the output terminal of the buffer.
摘要翻译：具有第一和第二输入端子和输出端子的缓冲器。缓冲器还包括具有输入端和输出端的快速边沿驱动器，输入端连接到缓冲器的第一输入端，输出端连接到缓冲器的输出端。提供具有输入端子和输出端子的屏蔽电路，输入端子连接到缓冲器的第二输入端子。该缓冲器还包括具有输入端和输出端的恢复电路，输入端连接到屏蔽电路的输出端，输出端连接到缓冲器的输出端。

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