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61. 发明授权

US5952866A CMOS output buffer protection circuit 失效
标题翻译： CMOS输出缓冲保护电路
公开(公告)号：US5952866A
公开(公告)日：1999-09-14
申请号：US069049
申请日：1998-04-28
申请人： Makeshwar Kothandaraman , Bernard Lee Morris , Bijit Thakorbhai Patel , Wayne E. Werner
发明人： Makeshwar Kothandaraman , Bernard Lee Morris , Bijit Thakorbhai Patel , Wayne E. Werner
IPC分类号： H03K17/08 , H03K19/003 , H03K19/0175 , H03L5/00
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： A low voltage CMOS output buffer protection circuit is configured to protect an associated output buffer from any high voltage signals (e.g., 5V) that may appear along a signal bus line. The protection circuit is also "hot-pluggable", meaning that the protection circuit will not draw any current when not powered (i.e., when VDD is not present). An on-chip reference voltage generator is used to provide a reference voltage VDD2 that will be essentially equal to VDD as long as VDD is present. When VDD is not present, VDD2 will track the signal appearing along the signal bus (PAD), remaining at least two diode drops below the PAD voltage.
摘要翻译：低电压CMOS输出缓冲保护电路被配置为保护相关联的输出缓冲器免受可能沿信号总线出现的任何高电压信号（例如5V）。保护电路也是“可热插拔”的，这意味着当不供电时（即当不存在VDD时），保护电路将不会产生任何电流。片上参考电压发生器用于提供基本上等于VDD的参考电压VDD2，只要存在VDD即可。当VDD不存在时，VDD2将跟踪沿着信号总线（PAD）出现的信号，至少保持两个二极管降低到PAD电压以下。

62. 发明授权

US08427223B2 Voltage level translator circuit for reducing jitter 有权
标题翻译：用于降低抖动的电压电平转换器电路
公开(公告)号：US08427223B2
公开(公告)日：2013-04-23
申请号：US13186310
申请日：2011-07-19
申请人： Pankaj Kumar , Pramod Parameswaran , Makeshwar Kothandaraman
发明人： Pankaj Kumar , Pramod Parameswaran , Makeshwar Kothandaraman
IPC分类号： H03L5/00
CPC分类号： H03K3/356113
摘要： A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node. A load circuit is coupled with the input stage, the load circuit being operative to at least temporarily store a signal at the first and/or second nodes which is indicative of a logical state of the input signal. An output stage connected with the second node is operative to generate an output signal which is indicative of a logical state of the input signal. The voltage level translator circuit further includes a compensation circuit connected with the output stage and operative to balance pull-up and pull-down propagation delays in the voltage level translator circuit as a function of a voltage at the first node.
摘要翻译：用于将参考第一电压源的输入信号转换为参考第二电压源的输出信号的电压电平转换器电路包括用于接收输入信号的输入级，输入级至少包括第一和第二节点，第二节点是第一节点处的电压的逻辑补码。负载电路与输入级耦合，负载电路可操作以至少临时存储指示输入信号的逻辑状态的第一和/或第二节点处的信号。与第二节点连接的输出级可操作以产生指示输入信号的逻辑状态的输出信号。电压电平转换器电路还包括与输出级连接的补偿电路，并且可操作以平衡电压电平转换器电路中的上拉和下拉传播延迟作为第一节点处的电压的函数。

63. 发明申请

US20130002267A1 Impedance Mismatch Detection Circuit 有权
标题翻译：阻抗不匹配检测电路
公开(公告)号：US20130002267A1
公开(公告)日：2013-01-03
申请号：US13171725
申请日：2011-06-29
申请人： Makeshwar Kothandaraman , Pankaj Kumar , Pramod Parameswaran
发明人： Makeshwar Kothandaraman , Pankaj Kumar , Pramod Parameswaran
IPC分类号： G01R27/28
CPC分类号： H03F3/45475 , H03F2203/45594
摘要： A comparison circuit for detecting impedance mismatch between pull-up and pull-down devices in a circuit to be monitored includes a comparator operative to receive first and second signals and to generate, as an output, a third signal indicative of a difference between the first and second signals. A first signal generator is operative to generate the first signal indicative of a difference between reference pull-up and pull-down currents that is scaled by a prescribed amount. The reference pull-up current is indicative of a current flowing through at least one corresponding pull-up transistor device in the circuit to be monitored. The pull-down reference current is indicative of a current flowing through at least one corresponding pull-down transistor device in the circuit to be monitored. A second signal generator connected with the second input of the comparator is operative to generate the second signal as a reference voltage defining a prescribed impedance mismatch threshold associated with the circuit to be monitored.
摘要翻译：用于检测待监测电路中的上拉和下拉器件之间的阻抗失配的比较电路包括一个比较器，用于接收第一和第二信号，并产生一个第三信号，该第三信号指示第一和第二信号之间的差值和第二信号。第一信号发生器用于产生表示参考上拉和下拉电流之间的差的第一信号，该下拉电流被缩放规定量。参考上拉电流指示流过待监测电路中的至少一个对应的上拉晶体管器件的电流。下拉参考电流表示流过待监测电路中的至少一个对应的下拉晶体管器件的电流。与比较器的第二输入端连接的第二信号发生器可操作以产生第二信号作为参考电压，该参考电压限定与待监视电路相关联的规定阻抗失配阈值。

64. 发明申请

US20110102048A1 BIAS VOLTAGE GENERATION TO PROTECT INPUT/OUTPUT (IO) CIRCUITS DURING A FAILSAFE OPERATION AND A TOLERANT OPERATION 有权
标题翻译：偏置电压发生保护输入/输出（IO）电路在故障安全操作和容错操作
公开(公告)号：US20110102048A1
公开(公告)日：2011-05-05
申请号：US12889440
申请日：2010-09-24
申请人： Pankaj Kumar , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande , John Kriz
发明人： Pankaj Kumar , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande , John Kriz
IPC分类号： H03L5/00
CPC分类号： H03K19/00315
摘要： A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad. The method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation.
摘要翻译：一种方法包括可控制地从电源电压产生第一偏置电压，使其处于集成电路的输入/输出（IO）核心器件的一个或多个构成的有源电路元件的工作电压的上容许限度内（ IC）与IO焊盘接口，并且可控制地从通过IO焊盘提供的外部电压产生第二偏置电压，使其在所述一个或多个构成的有源电路元件的工作电压的上容许限度内要与IO接口连接的IO内核设备。该方法还包括可控制地利用由IO核心产生的控制信号，以在驱动器操作模式期间从第一偏置电压导出输出偏置电压，或者在故障安全操作模式和容限操作模式期间导出第二偏置电压。

65. 发明授权

US07876132B1 Floating well circuit operable in a failsafe condition and a tolerant condition 有权
标题翻译：浮动井回路可在故障安全条件和容限条件下工作
公开(公告)号：US07876132B1
公开(公告)日：2011-01-25
申请号：US12580280
申请日：2009-10-16
申请人： Pankaj Kumar , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande , John Kriz
发明人： Pankaj Kumar , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande , John Kriz
IPC分类号： H03B1/00
CPC分类号： H03K17/08104 , H03K17/063 , H03K19/00315 , H03K2217/0018
摘要： A circuit includes a first comparator block configured to output a voltage equal to a higher of a supply voltage and a bias voltage, a second comparator block configured to output a voltage equal to a higher of the bias voltage and an external voltage supplied through an Input/Output (IO) pad, and a third comparator block configured to output a voltage equal to a higher of the output of the first comparator block and the output of the second comparator block. A voltage across one or more constituent active element(s) of each of the first comparator block, the second comparator block, and the third comparator block is within an upper tolerable limit thereof during each of a normal operation, a failsafe operation, and a tolerant operation.
摘要翻译：电路包括：第一比较器块，被配置为输出等于较高的电源电压和偏置电压的电压;第二比较器块，被配置为输出等于较高偏置电压的电压和通过输入提供的外部电压 /输出（IO）焊盘和第三比较器块，其被配置为输出等于第一比较器块的输出的较高的电压和第二比较器块的输出。第一比较器块，第二比较器块和第三比较器块中的每个的一个或多个构成有源元件上的电压在正常操作，故障安全操作和容忍操作。

66. 发明申请

US20080059142A1 Input/Output Buffer Information Specification (IBIS) Model Generation for Multi-chip Modules (MCM) and Similar Devices 有权
标题翻译：用于多芯片模块（MCM）和类似设备的输入/输出缓冲器信息规范（IBIS）模型生成
公开(公告)号：US20080059142A1
公开(公告)日：2008-03-06
申请号：US11469028
申请日：2006-08-31
申请人： James D. Chlipala , Makeshwar Kothandaraman , Nirav Patel , Venu Babu Ummalaneni
发明人： James D. Chlipala , Makeshwar Kothandaraman , Nirav Patel , Venu Babu Ummalaneni
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In one embodiment, the invention is a method for modeling electrical behavior of a packaged module having multiple integrated circuits (ICs), such as a multi-chip module (MCM). The method includes: (a) identifying one or more pin groups in the module, wherein a pin group comprises two or more buffers connected together and to a package-external pin, and (b) generating one or more corresponding unified behavioral models for the one or more pin groups based on the characteristics of the buffers of the one or more pin groups. The behavioral models are part of an integrated behavioral model file in accordance with the I/O buffer information specification (IBIS) standard.
摘要翻译：在一个实施例中，本发明是用于建模具有多个集成电路（IC）的封装模块的电气行为的方法，诸如多芯片模块（MCM）。该方法包括：（a）识别模块中的一个或多个引脚组，其中引脚组包括连接在一起的两个或多个缓冲器和封装外部引脚，以及（b）生成一个或多个对应的统一行为模型基于一个或多个引脚组的缓冲器的特性的一个或多个引脚组。行为模型是根据I / O缓冲区信息规范（IBIS）标准的集成行为模型文件的一部分。

67. 发明授权

US6147520A Integrated circuit having controlled impedance 失效
标题翻译：具有受阻阻抗的集成电路
公开(公告)号：US6147520A
公开(公告)日：2000-11-14
申请号：US993209
申请日：1997-12-18
申请人： Makeshwar Kothandaraman , Wayne E. Werner
发明人： Makeshwar Kothandaraman , Wayne E. Werner
IPC分类号： H01L27/04 , H01L21/822 , H03H7/24 , H03H7/38 , H03K19/00 , H03K19/003 , H04L25/02 , H03K5/22
CPC分类号： H04L25/0298 , H03H7/24 , H03K19/0005 , H03K19/00384 , H03H7/38 , H04L25/0276
摘要： An integrated circuit includes a controlled impedance that remains relatively constant with respect to variations in processing and temperature. The controlled impedance comprises a fixed resistor in parallel with one or more switchable resistors having a resistance value greater than that of the fixed resistance. Control circuitry includes a reference current generator. The reference current is flowed through a tracking resistor formed of the same material (e.g., doped polysilicon) in the same fabrication process as the fixed resistor. Comparators are used to monitor the voltage across the tracking resistor, and control the switching of the switchable resistors in order to obtain a desired effective resistance. Use of the inventive technique to provide a transmission line termination impedance is described in an illustrative embodiment.
摘要翻译：集成电路包括相对于处理和温度变化保持相对恒定的受控阻抗。受控阻抗包括与一个或多个具有大于固定电阻的电阻值的电阻值并联的固定电阻器。控制电路包括参考电流发生器。在与固定电阻器相同的制造工艺中，参考电流流过由相同材料（例如，掺杂多晶硅）形成的跟踪电阻器。比较器用于监视跟踪电阻上的电压，并控制可切换电阻的切换，以获得所需的有效电阻。在说明性实施例中描述了使用本发明的技术来提供传输线终端阻抗。

68. 发明授权

US6014039A CMOS high voltage drive output buffer 失效
标题翻译： CMOS高电压驱动输出缓冲器
公开(公告)号：US6014039A
公开(公告)日：2000-01-11
申请号：US67936
申请日：1998-04-28
申请人： Makeshwar Kothandaraman , Bernard Lee Morris , Bijit Thakorbhai Patel , Wayne E. Werner
发明人： Makeshwar Kothandaraman , Bernard Lee Morris , Bijit Thakorbhai Patel , Wayne E. Werner
IPC分类号： H03K17/08 , H03K19/003 , H03K19/0175 , H03K19/0948 , H03K19/0185
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： A CMOS high voltage drive output buffer that protects the drive stage from seeing relatively high voltages (e.g., 5 V) during "hot pluggable" conditions (that is, when the reference voltage VDD is not present). A transmission gate and clamping transistors are disposed around the output devices to provide the requisite protection. A backgate bias generator for use with P-channel devices is also disclosed that is capable of withstanding "hot pluggable" conditions.
摘要翻译： CMOS高电压驱动输出缓冲器，用于在“可热插拔”状态（即当不存在参考电压VDD时）保护驱动级不会看到相对较高的电压（例如5 V）。传输栅极和钳位晶体管围绕输出器件设置以提供必要的保护。还公开了一种用于P沟道器件的背栅偏置发生器，其能够承受“可热插拔”的条件。

69. 发明授权

US08441281B2 Current-mode logic buffer with enhanced output swing 有权
标题翻译：电流模式逻辑缓冲器，具有增强的输出摆幅
公开(公告)号：US08441281B2
公开(公告)日：2013-05-14
申请号：US13165500
申请日：2011-06-21
申请人： Makeshwar Kothandaraman , Pankaj Kumar , Paul K. Hartley , John Christopher Kriz
发明人： Makeshwar Kothandaraman , Pankaj Kumar , Paul K. Hartley , John Christopher Kriz
IPC分类号： H03K19/003 , H03K19/094 , H03K19/0175
CPC分类号： H03K19/09432 , H03K19/018528
摘要： A differential buffer circuit having increased output voltage swing includes a differential input stage including at least first and second transistors, the first and second transistors being operative to receive first and second signals, respectively. The buffer circuit further includes a bias stage connected between the differential input stage and a first voltage source. The bias stage is operative to generate a quiescent current as a function of a third signal supplied to the bias stage. A load circuit is connected between a second voltage source and the differential input stage, first and second differential outputs of the buffer circuit being generated at a junction between the load circuit and the differential input stage. The load circuit includes first and second switching elements coupled with the first and second transistors, respectively. The first switching element is operative to electrically connect the first differential output to the second voltage source when the first transistor is turned off. The second switching element is operative to electrically connect the second differential output to the second voltage source when the second transistor is turned off.
摘要翻译：具有增加的输出电压摆幅的差分缓冲电路包括至少包括第一和第二晶体管的差分输入级，第一和第二晶体管分别用于接收第一和第二信号。缓冲电路还包括连接在差分输入级与第一电压源之间的偏置级。偏置级用于产生作为提供给偏置级的第三信号的函数的静态电流。负载电路连接在第二电压源和差分输入级之间，缓冲电路的第一和第二差分输出在负载电路和差分输入级之间的结点处产生。负载电路分别包括与第一和第二晶体管耦合的第一和第二开关元件。当第一晶体管截止时，第一开关元件可操作以将第一差分输出电连接到第二电压源。当第二晶体管截止时，第二开关元件可操作以将第二差分输出电连接到第二电压源。

70. 发明申请

US20130021085A1 Voltage Level Translator Circuit for Reducing Jitter 有权
标题翻译：用于减少抖动的电压电平转换器电路
公开(公告)号：US20130021085A1
公开(公告)日：2013-01-24
申请号：US13186310
申请日：2011-07-19
申请人： Pankaj Kumar , Pramod Parameswaran , Makeshwar Kothandaraman
发明人： Pankaj Kumar , Pramod Parameswaran , Makeshwar Kothandaraman
IPC分类号： H03L5/00
CPC分类号： H03K3/356113
摘要： A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node. A load circuit is coupled with the input stage, the load circuit being operative to at least temporarily store a signal at the first and/or second nodes which is indicative of a logical state of the input signal. An output stage connected with the second node is operative to generate an output signal which is indicative of a logical state of the input signal. The voltage level translator circuit further includes a compensation circuit connected with the output stage and operative to balance pull-up and pull-down propagation delays in the voltage level translator circuit as a function of a voltage at the first node.
摘要翻译：用于将参考第一电压源的输入信号转换为参考第二电压源的输出信号的电压电平转换器电路包括用于接收输入信号的输入级，输入级至少包括第一和第二节点，第二节点是第一节点处的电压的逻辑补码。负载电路与输入级耦合，负载电路可操作以至少临时存储指示输入信号的逻辑状态的第一和/或第二节点处的信号。与第二节点连接的输出级可操作以产生指示输入信号的逻辑状态的输出信号。电压电平转换器电路还包括与输出级连接的补偿电路，并且可操作以平衡电压电平转换器电路中的上拉和下拉传播延迟作为第一节点处的电压的函数。

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