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61. 发明申请

US20080158932A1 Memory having bit line with resistor(s) between memory cells 有权
标题翻译：存储器与存储器单元之间的电阻器具有位线
公开(公告)号：US20080158932A1
公开(公告)日：2008-07-03
申请号：US11648399
申请日：2006-12-28
申请人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
发明人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C11/413
摘要： For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，集成电路可以包括集成电路上的存储器阵列和集成电路上的访问控制电路。存储器阵列可以具有沿着位线的一个或多个电阻器的位线，并且可以具有沿着位线的多个位置处耦合到位线的多个存储器单元。沿着位线的至少一个电阻器可以在存储器单元耦合到位线的两个位置之间。访问控制电路可以是选择耦合到位线的存储器单元并且感测来自所选存储单元的位线上的信号。还公开了其他实施例。

62. 发明授权

US06801463B2 Method and apparatus for leakage compensation with full Vcc pre-charge 有权
标题翻译：具有全Vcc预充电的漏电补偿方法和装置
公开(公告)号：US06801463B2
公开(公告)日：2004-10-05
申请号：US10273627
申请日：2002-10-17
申请人： Muhammad M. Khellah , Yibin Ye , Dinesh Somasekhar , Vivek De
发明人： Muhammad M. Khellah , Yibin Ye , Dinesh Somasekhar , Vivek De
IPC分类号： G11C700
CPC分类号： G11C7/12
摘要： A leakage compensation approach enabling full VCC precharge. An array of memory cells is coupled between a pair of bit lines. A precharge circuit precharges the pair of bit lines to substantially a supply voltage level and a leakage compensation circuit supplies a first compensation current to a first one of the bit lines to substantially compensate for leakage current supplied by the first bit line during a memory access operation directed to one of the plurality of memory cells.
摘要翻译：一种允许全VCC预充电的漏电补偿方式。存储器单元阵列耦合在一对位线之间。预充电电路将该对位线预充电到基本上的电源电压电平，并且泄漏补偿电路向位线中的第一位提供第一补偿电流，以在存储器访问操作期间基本上补偿由第一位线提供的泄漏电流指向多个存储器单元中的一个。

63. 发明授权

US08006164B2 Memory cell supply voltage control based on error detection 有权
标题翻译：基于错误检测的存储单元电源电压控制
公开(公告)号：US08006164B2
公开(公告)日：2011-08-23
申请号：US11542007
申请日：2006-09-29
申请人： Khellah Muhammad , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
发明人： Khellah Muhammad , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G11C11/4125 , G11C11/417 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5004
摘要： For one embodiment, an apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error. Other embodiments have one or more other features.
摘要翻译：对于一个实施例，一种装置包括存储器电路，其包括存储器单元，用于检测由存储器电路的存储器单元存储的数据中的错误的错误检测电路，以及用于增加基于存储器电路的一个或多个存储器单元的电源电压的电源电压控制电路至少部分是检测到的错误。其他实施例具有一个或多个其他特征。

64. 发明授权

US07199617B1 Level shifter 有权
标题翻译：电平移位器
公开(公告)号：US07199617B1
公开(公告)日：2007-04-03
申请号：US11111060
申请日：2005-04-21
申请人： Gerhard Schrom , Dinesh Somasekhar , Peter Hazucha , Stephen Tang , Vivek De
发明人： Gerhard Schrom , Dinesh Somasekhar , Peter Hazucha , Stephen Tang , Vivek De
IPC分类号： H04K19/094 , H04K19/0175
CPC分类号： H03K19/018528
摘要： A level shifting device comprises an input stage, a cascode stage, a cross-coupled stage, and an output stage. The input stage may receive a data signal or binary logic input in a first data range, a complement of the data signal, and a first voltage. The cascode stage may receive a first voltage and may be connected to the input stage. The cross-coupled stage may be adapted to isolate the first voltage and may be connected to the cascode stage. The output stage may receive a second voltage, provide an output, and be connected to the cross-coupled stage. The cascode stage may be adapted to provide the first voltage as the output when the logic input is a first value and provide the second voltage as the output when the logic input is a second value. Other embodiments are also claimed and described.
摘要翻译：电平移位装置包括输入级，共源共栅级，交叉耦合级和输出级。输入级可以在第一数据范围内接收数据信号或二进制逻辑输入，数据信号的补码和第一电压。共源共栅级可以接收第一电压并且可以连接到输入级。交叉耦合级可以适于隔离第一电压并且可以连接到共源共栅级。输出级可以接收第二电压，提供输出，并连接到交叉耦合级。当逻辑输入是第一值时，共源共栅级可以适于提供第一电压作为输出，并且当逻辑输入是第二值时提供第二电压作为输出。还要求保护和描述其它实施例。

65. 发明申请

US20060065962A1 Control circuitry in stacked silicon 审中-公开
标题翻译：堆叠硅中的控制电路
公开(公告)号：US20060065962A1
公开(公告)日：2006-03-30
申请号：US10954256
申请日：2004-09-29
申请人： Siva Narendra , James Tschanz , Vivek De , Shekhar Borkar
发明人： Siva Narendra , James Tschanz , Vivek De , Shekhar Borkar
IPC分类号： H01L23/02
CPC分类号： H01L25/18 , H01L2224/05001 , H01L2224/05026 , H01L2224/0557 , H01L2224/05571 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/00 , H01L2224/05005 , H01L2224/05541 , H01L2224/05599
摘要： Apparatus, system and method for managing power of a main circuitry disposed on a main substrate using a control circuitry disposed on a control substrate, in a stacked relationship with the main substrate, are described herein.
摘要翻译：这里描述了使用设置在控制基板上的与主基板堆叠关系的设置在主基板上的主电路的电力的装置，系统和方法。

66. 发明申请

US20060071650A1 CPU power delivery system 审中-公开
标题翻译： CPU供电系统
公开(公告)号：US20060071650A1
公开(公告)日：2006-04-06
申请号：US10954464
申请日：2004-09-30
申请人： Siva Narendra , Howard Wilson , Donald Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek De , Shekhar Borkar
发明人： Siva Narendra , Howard Wilson , Donald Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek De , Shekhar Borkar
IPC分类号： G05F1/40
CPC分类号： G06F1/26 , G06F1/189 , H01L25/16 , H01L25/18 , H01L2224/16145 , H01L2924/00014 , H01L2924/01068 , H01L2924/15311 , H01L2924/3011 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator/converter die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种中央处理单元（CPU）。 CPU包括CPU管芯; 以及以三维封装布局结合到CPU管芯的电压调节器/转换器管芯。

67. 发明申请

US20060071648A1 Power management integrated circuit 有权
标题翻译：电源管理集成电路
公开(公告)号：US20060071648A1
公开(公告)日：2006-04-06
申请号：US10955383
申请日：2004-09-30
申请人： Siva Narendra , James Tschanz , Howard Wilson , Donald Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek De , Shekhar Borkar
发明人： Siva Narendra , James Tschanz , Howard Wilson , Donald Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek De , Shekhar Borkar
IPC分类号： G05F1/00
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a power management die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种中央处理单元（CPU）。 CPU包括CPU管芯; 以及以三维封装布局结合到CPU裸片的电源管理裸片。

68. 发明申请

US20070260848A1 Power mangement integrated circuit 有权
标题翻译：电力管理集成电路
公开(公告)号：US20070260848A1
公开(公告)日：2007-11-08
申请号：US11825252
申请日：2007-07-03
申请人： Siva Narendra , James Tschanz , Howard Wilson , Donald Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek De , Shekhar Borkar
发明人： Siva Narendra , James Tschanz , Howard Wilson , Donald Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek De , Shekhar Borkar
IPC分类号： G06F15/00 , H01L21/50 , H01L23/34
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。

69. 发明申请

US20060099734A1 CPU power delivery system 有权
标题翻译： CPU供电系统
公开(公告)号：US20060099734A1
公开(公告)日：2006-05-11
申请号：US10955746
申请日：2004-09-30
申请人： Siva Narendra , Howard Wilson , Donald Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek De , Shekhar Borkar
发明人： Siva Narendra , Howard Wilson , Donald Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek De , Shekhar Borkar
IPC分类号： H01L21/50
CPC分类号： H01L25/18 , G06F1/189 , G06F1/26 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2924/00011 , H01L2924/00014 , H01L2924/3011 , H01L2224/0401
摘要： A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种中央处理单元（CPU）。 CPU包括CPU管芯; 以及以三维封装布局结合到CPU裸片的电压调节器芯片。

70. 发明申请

US20120110266A1 DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS 失效
标题翻译：在低电压运行期间禁用高速缓存部分
公开(公告)号：US20120110266A1
公开(公告)日：2012-05-03
申请号：US13342016
申请日：2011-12-31
申请人： Christopher Wilkerson , M. Muhammad Khellah , Vivek De , Ming Y. Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , M. Muhammad Khellah , Vivek De , Ming Y. Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F1/3203 , G06F1/3275 , G06F1/3296 , G06F12/0864 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
摘要翻译：描述了在低电压操作期间禁用一个或多个高速缓存部分的方法和装置。在一些实施例中，一个或多个额外的比特可以用于高速缓存的一部分，其指示高速缓存的部分是否能够在Vccmin等级或更低的值下运行。还描述和要求保护其他实施例。

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