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61. 发明授权

US08815734B2 Use of gas cluster ion beam to reduce metal void formation in interconnect structures 有权
标题翻译：使用气体簇离子束来减少互连结构中的金属空隙形成
公开(公告)号：US08815734B2
公开(公告)日：2014-08-26
申请号：US13290577
申请日：2011-11-07
申请人： Kangguo Cheng , Junli Wang , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Kangguo Cheng , Junli Wang , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76804 , H01L21/76814 , H01L21/76825 , H01L21/76865 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A gas cluster ion beam process is used to reduce and/or even eliminate metal void formation in an interconnect structure. In one embodiment, gas cluster ion beam etching forms a chamfer opening in an interconnect dielectric material. In another embodiment, gas cluster ion beam etching reduces the overhang profile of a diffusion barrier or a multilayered stack of a diffusion barrier and a plating seed layer that is formed within an opening located in an interconnect dielectric material. In yet another embodiment, a gas cluster ion beam process deactivates a surface of an interconnect dielectric material that is located at upper corners of an opening that is formed therein. In this embodiment, the gas cluster ion beam process deposits a material that deactivates the upper corners of each opening that is formed into an interconnect dielectric material.
摘要翻译：使用气体簇离子束工艺来减少和/或甚至消除互连结构中的金属空隙形成。在一个实施例中，气体簇离子束蚀刻在互连电介质材料中形成倒角开口。在另一个实施方案中，气体簇离子束蚀刻减少扩散阻挡层或扩散阻挡层的多层堆叠和形成在位于互连电介质材料中的开口内的电镀种子层的悬垂分布。在另一个实施例中，气体团簇离子束过程使位于其中形成的开口的上角的互连电介质材料的表面失活。在该实施例中，气体簇离子束处理沉积了使形成为互连电介质材料的每个开口的上角失活的材料。

62. 发明授权

US08796773B2 Metal gate and high-K dielectric devices with PFET channel SiGe 有权
标题翻译：具有PFET通道SiGe的金属栅极和高K电介质器件
公开(公告)号：US08796773B2
公开(公告)日：2014-08-05
申请号：US13539700
申请日：2012-07-02
申请人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong
发明人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong
IPC分类号： H01L27/12
CPC分类号： H01L21/823807 , H01L21/823842 , H01L21/823857
摘要： In a circuit structure, PFET devices have a gate dielectric including a high-k dielectric, a gatestack with a metal, a p-source/drain and silicide layer formed over the p-source/drain; NFET devices include a gate dielectric including a high-k dielectric, a gatestack with a metal, an n-source/drain and silicide layer formed over the n-source/drain. An epitaxial SiGe is present underneath and in direct contact with the PFET gate dielectric, while the epitaxial SiGe is absent underneath the NFET gate dielectric.
摘要翻译：在电路结构中，PFET器件具有栅极电介质，其包括高k电介质，具有金属的栅格，p源极/漏极和形成在p源极/漏极上的硅化物层; NFET器件包括包括高k电介质的栅极电介质，具有金属的糖饼，在n源极/漏极上形成的n源极/漏极和硅化物层。外延SiGe存在于PFET栅极电介质的下面并与PFET栅极电介质直接接触，而外延SiGe不存在于NFET栅极电介质下方。

63. 发明授权

US08466443B2 Voltage sensitive resistor (VSR) read only memory 失效
标题翻译：电压敏感电阻（VSR）只读存储器
公开(公告)号：US08466443B2
公开(公告)日：2013-06-18
申请号：US12827197
申请日：2010-06-30
申请人： Terence L. Kane , Yun-Yu Wang , Keith Kwong Hon Wong
发明人： Terence L. Kane , Yun-Yu Wang , Keith Kwong Hon Wong
IPC分类号： H01L29/02
CPC分类号： H01L45/1616 , G11C17/14 , H01C7/1013 , H01C7/105 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a voltage sensitive resistor (VSR) write once (WO) read only memory (ROM) device which includes a semiconductor device and a VSR connected to the semiconductor device. The VSR WO ROM device is a write once read only device. The VSR includes a CVD titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by an order of 102, more preferably 103 and most preferably 104 when a predetermined voltage and current are applied to the VSR. A plurality of the VSR WO ROM devices may be arranged to form a high density programmable logic circuit in a 3-D stack. Also disclosed are methods to form the VSR WO ROM device.
摘要翻译：公开了一种包括半导体器件和连接到半导体器件的VSR的一次（WO）只读存储器（ROM）器件的电压敏感电阻器（VSR）。 VSR WO ROM设备是一次写入只读设备。 VSR包括具有残留钛 - 碳键合的CVD氮化钛层，使得VSR是形成的电阻的，并且当预定的电压和电流被施加到电阻时，可以变得更小的电阻性为102，更优选为103，最优选为104。 VSR。多个VSR WO ROM器件可以被布置成在3-D堆栈中形成高密度可编程逻辑电路。还公开了形成VSR WO ROM器件的方法。

64. 发明授权

US08421228B2 Structure and methods of forming contact structures 有权
标题翻译：形成接触结构的结构和方法
公开(公告)号：US08421228B2
公开(公告)日：2013-04-16
申请号：US13405443
申请日：2012-02-27
申请人： Ying Li , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Ying Li , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76844 , H01L21/76846 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A contact structure and a method of forming the contact structure. The structure includes: a silicide layer on and in direct physical contact with a top substrate surface of a substrate; an electrically insulating layer on the substrate; and an aluminum plug within the insulating layer. The aluminum plug has a thickness not exceeding 25 nanometers in a direction perpendicular to the top substrate surface. The aluminum plug extends from a top surface of the silicide layer to a top surface of the insulating layer. The aluminum plug is in direct physical contact with the top surface of the silicide layer and is in direct physical contact with the silicide layer. The method includes: forming the silicide layer on and in direct physical contact with the top substrate surface of the substrate; forming the electrically insulating layer on the substrate; and forming the aluminum plug within the insulating layer.
摘要翻译：接触结构和形成接触结构的方法。该结构包括：与衬底的顶部衬底表面直接物理接触的硅化物层; 基板上的电绝缘层; 和绝缘层内的铝塞。该铝塞的垂直于顶部基板表面的方向的厚度不超过25纳米。铝塞从硅化物层的顶表面延伸到绝缘层的顶表面。铝插塞与硅化物层的顶表面直接物理接触并与硅化物层直接物理接触。该方法包括：在衬底的顶部衬底表面上直接物理接触形成硅化物层; 在基板上形成电绝缘层; 以及在所述绝缘层内形成所述铝塞。

65. 发明申请

US20130062677A1 SELF-ALIGNED BOTTOM PLATE FOR METAL HIGH-K DIELECTRIC METAL INSULATOR METAL (MIM) EMBEDDED DYNAMIC RANDOM ACCESS MEMORY 有权
标题翻译：用于金属高K介电金属绝缘体金属（MIM）嵌入式动态随机存取存储器的自对准底板
公开(公告)号：US20130062677A1
公开(公告)日：2013-03-14
申请号：US13228767
申请日：2011-09-09
申请人： Zhengwen Li , Damon B. Farmer , Michael P. Chudzik , Keith Kwong Hon Wong , Jian Yu , Zhen Zhang , Chengwen Pei
发明人： Zhengwen Li , Damon B. Farmer , Michael P. Chudzik , Keith Kwong Hon Wong , Jian Yu , Zhen Zhang , Chengwen Pei
IPC分类号： H01L21/20 , H01L27/06
CPC分类号： H01L27/10829 , H01L21/84 , H01L27/10861 , H01L27/1203 , H01L28/91 , H01L29/945
摘要： A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.
摘要翻译：提供一种存储器件和形成存储器件的方法，其包括具有金属半导体合金的下电极的电容器。在一个实施例中，存储器件包括存在于半导体衬底中的沟槽，其包括在掩埋介电层顶部上的绝缘（SOI）半导体层，其中所述掩埋介电层位于基底半导体层的顶部。电容器存在于沟槽中，其中电容器包括金属半导体合金的下电极，其具有与基底半导体层的上表面自对准的上边缘，高k电介质节点层和上层金属电极。存储器件还包括与电容器电连通的传输晶体管。

66. 发明授权

US08298882B2 Metal gate and high-K dielectric devices with PFET channel SiGe 有权
标题翻译：具有PFET通道SiGe的金属栅极和高K电介质器件
公开(公告)号：US08298882B2
公开(公告)日：2012-10-30
申请号：US12563032
申请日：2009-09-18
申请人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong
发明人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/823842 , H01L21/823857
摘要： Fabricating of semiconductor devices includes: depositing epitaxially a SiGe layer onto both NFET and PFET portions of a Si surface; blanket disposing a first sequence of layers over the SiGe layer including a high-k dielectric and a metal, incorporating the first sequence of layers into the gatestacks and gate insulators of both NFET devices and PFET devices; the first sequence of layers is selected to yield desired device parameter values for the PFET devices; removing the gatestack, the gate dielectric, and the SiGe layer for the NFET devices, re-forming the NFET devices by deploying a second sequence of layers that include a second high-k dielectric and a second metal; the second sequence of layers is selected to yield desired device parameter values for the NFET devices.
摘要翻译：半导体器件的制造包括：在Si表面的NFET和PFET部分上外延沉积SiGe层; 在包括高k电介质和金属的SiGe层上布置第一层序列，将第一层序列结合到两个NFET器件和PFET器件的栅极绝缘体和栅极绝缘体中; 选择层的第一序列以产生PFET器件的期望的器件参数值; 去除用于NFET器件的盖板，栅极电介质和SiGe层，通过布置包括第二高k电介质和第二金属的第二层序列来重新形成NFET器件; 选择第二层次序列以产生NFET器件的期望的器件参数值。

67. 发明申请

US20120256277A1 SEMICONDUCTOR DEVICE EXHIBITING REDUCED PARASITICS AND METHOD FOR MAKING SAME 有权
标题翻译：半导体器件展示减少的PARASITICS及其制造方法
公开(公告)号：US20120256277A1
公开(公告)日：2012-10-11
申请号：US13083893
申请日：2011-04-11
申请人： Bruce B. Doris , Kangguo Cheng , Keith Kwong Hon Wong
发明人： Bruce B. Doris , Kangguo Cheng , Keith Kwong Hon Wong
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/518 , H01L27/24 , H01L29/41775 , H01L29/42376 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device includes a substrate and a gate stack disposed on the substrate. An upper layer of the gate stack is a metal gate conductor and a lower layer of the gate stack is a gate dielectric. A gate contact is in direct contact with the metal gate conductor.
摘要翻译：半导体器件包括衬底和设置在衬底上的栅极堆叠。栅极堆叠的上层是金属栅极导体，栅极叠层的下层是栅极电介质。栅极触点与金属栅极导体直接接触。

68. 发明申请

US20120187420A1 STRUCTURE AND METHOD TO MAKE REPLACEMENT METAL GATE AND CONTACT METAL 有权
标题翻译：结构和方法替代金属门和接触金属
公开(公告)号：US20120187420A1
公开(公告)日：2012-07-26
申请号：US13427963
申请日：2012-03-23
申请人： Zhengwen Li , Michael P. Chudzik , Unoh Kwon , Filippos Papadatos , Andrew H. Simon , Keith Kwong Hon Wong
发明人： Zhengwen Li , Michael P. Chudzik , Unoh Kwon , Filippos Papadatos , Andrew H. Simon , Keith Kwong Hon Wong
IPC分类号： H01L29/16 , H01L29/78
CPC分类号： H01L23/485 , H01L21/28088 , H01L21/28202 , H01L21/76283 , H01L21/76877 , H01L21/823842 , H01L21/823871 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： An electrical device is provided that in one embodiment includes a p-type semiconductor device having a first gate structure that includes a gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.
摘要翻译：提供了一种电气装置，其在一个实施例中包括具有第一栅极结构的p型半导体器件，该第一栅极结构包括存在于半导体衬底上的栅极电介质，p型功函数金属层，由钛构成的金属层和铝和由铝构成的金属填充物。 n型半导体器件也存在于半导体衬底上，该半导体衬底包括第二栅极结构，其包括栅极电介质，由钛和铝构成的金属层以及由铝组成的金属填充物。层间电介质存在于半导体衬底上。层间电介质包括到p型和n型半导体器件的源区和漏区的互连。互连由钛和铝构成的金属层和由铝组成的金属填充物构成。本公开还提供了形成上述结构的方法。

69. 发明申请

US20120181630A1 REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT 有权
标题翻译：具有降低闸门泄漏电流的更换门
公开(公告)号：US20120181630A1
公开(公告)日：2012-07-19
申请号：US13006656
申请日：2011-01-14
申请人： Takashi Ando , Michael P. Chudzik , Rishikesh Krishnan , Siddarth A. Krishnan , Unoh Kwon , Keith Kwong Hon Wong
发明人： Takashi Ando , Michael P. Chudzik , Rishikesh Krishnan , Siddarth A. Krishnan , Unoh Kwon , Keith Kwong Hon Wong
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28008 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/66545 , H01L29/66606 , H01L29/7833 , H01L29/7843
摘要： Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.
摘要翻译：提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。金属化合物层包括功函数约4.4eV或更低的材料，并且可以包括选自碳化钽和铪硅合金的材料。因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。

70. 发明申请

US20120129340A1 ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION 有权
公开(公告)号：US20120129340A1
公开(公告)日：2012-05-24
申请号：US13360248
申请日：2012-01-27
申请人： Terence L. Kane , Michael P. Tenney , Yun-Yu Wang , Keith Kwong Hon Wong
发明人： Terence L. Kane , Michael P. Tenney , Yun-Yu Wang , Keith Kwong Hon Wong
IPC分类号： H01L21/283
CPC分类号： H01L23/5252 , H01L21/76823 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.

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