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61. 发明申请

US20110099591A1 SECURE WIRELESS PAIRING OF DIGITAL TV SHORT-RANGE TRANSMITTER AND RECEIVER 审中-公开
标题翻译：数字电视短距离发射机和接收机的安全无线配对
公开(公告)号：US20110099591A1
公开(公告)日：2011-04-28
申请号：US12607894
申请日：2009-10-28
申请人： Men Long , David M. Durham
发明人： Men Long , David M. Durham
IPC分类号： H04N7/18 , H04W84/02 , H04N5/66 , H04N7/167 , H04L9/08
CPC分类号： H04N7/1675 , H04L9/0825 , H04L63/0442 , H04L2209/60 , H04L2209/80 , H04N21/4122 , H04N21/43637 , H04N21/4367 , H04N21/443 , H04W12/00504 , H04W12/00522 , H04W12/04
摘要： Embodiments of wireless display of digital content include transmission using a television transmission standard, such as a set of standards defined by the Advanced Television Systems Committee (ATSC) for digital television (TV) transmissions. The digital content is transmitted in a short range wireless network. In some embodiments, an encryption technique is applied to add security allowing decryption by a digital television using a firmware update, allowing retrofitting of security to devices currently deployed.
摘要翻译：数字内容的无线显示的实施例包括使用诸如由用于数字电视（TV）传输的高级电视系统委员会（ATSC）定义的一组标准的电视传输标准的传输。数字内容在短距离无线网络中传输。在一些实施例中，应用加密技术来增加允许使用固件更新的数字电视进行解密的安全性，允许将当前部署的设备改装为安全性。

62. 发明申请

US20090172341A1 USING A MEMORY ADDRESS TRANSLATION STRUCTURE TO MANAGE PROTECTED MICRO-CONTEXTS 有权
标题翻译：使用存储器地址转换结构来管理保护的MICR-CONTEXTS
公开(公告)号：US20090172341A1
公开(公告)日：2009-07-02
申请号：US11967458
申请日：2007-12-31
申请人： David M. Durham , Uday R. Savagaonkar , Ravi Sahita
发明人： David M. Durham , Uday R. Savagaonkar , Ravi Sahita
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F9/461 , G06F12/1036 , G06F12/109 , G06F12/145 , G06F2212/651
摘要： Embodiments of an invention for using a memory address translation structure to manage protected micro-contexts are disclosed. In one embodiment, an apparatus includes an interface and memory management logic. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated address to a memory address. The memory management logic includes a storage location, a series of translation stages, and determination logic. The storage location is to store an address of a data structure for the first translation stage. Each of the translation stages includes translation logic to find an entry in a data structure based on a portion of the untranslated address. Each entry is to store an address of a different data structure for the first translation stage, an address of a data structure for a successive translation stage, or the physical address. The determination logic is to determine whether an entry is storing an address of a different data structure for the first translation stage.
摘要翻译：公开了使用存储器地址转换结构来管理受保护的微上下文的发明的实施例。在一个实施例中，一种装置包括接口和存储器管理逻辑。该接口是执行一个事务来从内存中获取信息。存储器管理逻辑将非翻译地址转换为存储器地址。存储器管理逻辑包括存储位置，一系列转换级和确定逻辑。存储位置是存储用于第一翻译阶段的数据结构的地址。每个翻译阶段包括翻译逻辑，以基于未翻译地址的一部分在数据结构中找到条目。每个条目是存储用于第一翻译阶段的不同数据结构的地址，用于连续翻译阶段的数据结构的地址或物理地址。确定逻辑是确定条目是否存储用于第一翻译阶段的不同数据结构的地址。

63. 发明授权

US07483423B2 Authenticity of communications traffic 有权
标题翻译：通信流量的真实性
公开(公告)号：US07483423B2
公开(公告)日：2009-01-27
申请号：US11096843
申请日：2005-03-30
申请人： Karanvir Grewal , David M. Durham
发明人： Karanvir Grewal , David M. Durham
IPC分类号： H04L12/56
CPC分类号： H04L63/123
摘要： Provided are a techniques for storing information in a packet. A data integrity operation is performed over one portion of the packet to calculate an integrity check value using a secret key. The data transformation operation is performed over another selectable portion of the packet to store the integrity check value in the other portion of the packet, without increasing a size of the packet.Other embodiments are described and claimed.
摘要翻译：提供了用于在信息包中存储信息的技术。在分组的一部分上执行数据完整性操作，以使用密钥来计算完整性校验值。在分组的另一可选部分上执行数据变换操作，以将完整性校验值存储在分组的其他部分中，而不增加分组的大小。描述和要求保护其他实施例。

64. 发明授权

US07463638B2 Up-tree topology trace for network route tracing 失效
标题翻译：用于网络路由跟踪的up-tree拓扑跟踪
公开(公告)号：US07463638B2
公开(公告)日：2008-12-09
申请号：US10795791
申请日：2004-03-08
申请人： David M. Durham , Russell J. Fenger
发明人： David M. Durham , Russell J. Fenger
IPC分类号： H04L12/28 , G06F15/16
CPC分类号： H04L45/02 , H04L45/48
摘要： A network route tracing system traces a path through a network and identifiesnetwork components and communications links affected by the path. According to one embodiment of the present invention, a route is traced between two hosts in a network. The network is represented as a logical tree having a plurality of nodes. Each one of the nodes corresponds to a component in the network and each non-root node has a parent node. Two nodes are identified in the logical tree. A first node corresponds to a first host and a second node corresponding to a second host. If one of the two nodes exists at a lower level of the logical tree, then a first path is traced from the first node at the lower level to the parent node at a higher level until the parent node is at a same level of the logical tree as the second node. The first path is further traced up the logical tree from the parent node and a second path is traced up the logical tree from the second node until the first path and the second path meet at a same node.
摘要翻译：网络路由跟踪系统通过网络跟踪路径，并识别受路径影响的网络组件和通信链路。根据本发明的一个实施例，在网络中的两个主机之间追踪路由。网络被表示为具有多个节点的逻辑树。每个节点对应于网络中的一个组件，每个非根节点都有一个父节点。在逻辑树中标识两个节点。第一节点对应于第一主机和对应于第二主机的第二节点。如果两个节点中的一个存在于逻辑树的较低层，则将第一路径从较低级别的第一节点追溯到较高级别的父节点，直到父节点处于逻辑层的相同级别树作为第二个节点。第一条路径从父节点进一步跟踪逻辑树，第二条路径从第二个节点追溯到逻辑树，直到第一条路径和第二条路径在同一个节点相交。

65. 发明申请

US20080244758A1 SYSTEMS AND METHODS FOR SECURE ASSOCIATION OF HARDWARD DEVICES 审中-公开
标题翻译：硬件设备安全协调的系统和方法
公开(公告)号：US20080244758A1
公开(公告)日：2008-10-02
申请号：US11694548
申请日：2007-03-30
申请人： Ravi Sahita , Hormuzd M. Khosravi , Uday Savagaonkar , David M. Durham
发明人： Ravi Sahita , Hormuzd M. Khosravi , Uday Savagaonkar , David M. Durham
IPC分类号： G06F1/26 , G06F9/26
CPC分类号： G06F21/6218 , G06F21/57 , G06F21/70
摘要： An apparatus to protect one or more hardware devices from unauthorized software access is described herein and comprises, in one embodiment, a virtual machine manager, a memory protection module and an integrity measurement manager. In a further embodiment, a method of providing secure access to one or more hardware devices may include, modifying a page table, verifying the integrity of a device driver, and providing memory protection to the device driver if the device driver is verified.
摘要翻译：本文描述了保护一个或多个硬件设备免受未经授权的软件访问的装置，并且在一个实施例中包括虚拟机管理器，存储器保护模块和完整性测量管理器。在另一实施例中，提供对一个或多个硬件设备的安全访问的方法可以包括：修改页表，验证设备驱动程序的完整性，以及如果设备驱动程序被验证，则向设备驱动程序提供存储器保护。

66. 发明申请

US20080083030A1 Method and apparatus for run-time in-memory patching of code from a service processor 有权
标题翻译：从服务处理器的代码运行时内存补丁的方法和装置
公开(公告)号：US20080083030A1
公开(公告)日：2008-04-03
申请号：US11540373
申请日：2006-09-29
申请人： David M. Durham , Hormuzd M. Khosravi , Travis Schluessler , Ravi Sahita , Uday R. Savagaonkar
发明人： David M. Durham , Hormuzd M. Khosravi , Travis Schluessler , Ravi Sahita , Uday R. Savagaonkar
IPC分类号： G06F12/14
CPC分类号： G06F8/656
摘要： Methods and apparatuses enable in-memory patching of a program loaded in volatile memory. A service processor identifies a program to be patched and an associated patch for the program. The patch is loaded into memory, including applying relocation fix-ups to the patch. The service processor directs the program to the patch in place of the segment of the program to be patched. The program implements the patch while maintaining program state, and without suspending execution of the program.
摘要翻译：方法和装置使得能够在加载在易失性存储器中的程序的内存中修补。服务处理器识别要修补的程序和程序的相关修补程序。修补程序加载到内存中，包括将修补程序应用于修补程序。服务处理器将程序引导到补丁代替要修补的程序的段。该程序在维护程序状态的同时实现补丁，并且不会暂停程序的执行。

67. 发明授权

US07254133B2 Prevention of denial of service attacks 有权
标题翻译：防止拒绝服务攻击
公开(公告)号：US07254133B2
公开(公告)日：2007-08-07
申请号：US10196541
申请日：2002-07-15
申请人： Priya Govindarajan , David M. Durham
发明人： Priya Govindarajan , David M. Durham
IPC分类号： H04L12/28
CPC分类号： H04L63/1458 , H04L29/06 , H04L69/16 , H04L69/163
摘要： Denial of service type attacks are attacks where the nature of a system used to establish communication sessions is exploited to prevent the establishment of sessions. For example, to establish a Transmission Control Protocol (TCP)/Internet Protocol (IP) communication session, a three-way handshake is performed between communication endpoints. When a connection request is received, resources are allocated towards establishing the communication session. Malicious entities can attack the handshake by repeatedly only partially completing the handshake, causing the receiving endpoint to run out of resources for allocating towards establishing sessions, thus preventing legitimate connections. Illustrated embodiments overcome such attacks by delaying allocating resources until after the three-way handshake is successfully completed.
摘要翻译：拒绝服务类型攻击是攻击，其中用于建立通信会话的系统的性质被利用来阻止建立会话。例如，为了建立传输控制协议（TCP）/因特网协议（IP）通信会话，在通信端点之间执行三次握手。当接收到连接请求时，分配资源来建立通信会话。恶意实体可以通过重复仅部分完成握手来攻击握手，导致接收端点用尽资源以分配建立会话，从而防止合法连接。示例性实施例通过延迟分配资源来克服这种攻击，直到三次握手成功完成。

68. 发明授权

US07194556B2 Method and apparatus for high accuracy distributed time synchronization using processor tick counters 失效
标题翻译：使用处理器刻度计数器的高精度分布式时间同步的方法和装置
公开(公告)号：US07194556B2
公开(公告)日：2007-03-20
申请号：US09823070
申请日：2001-03-30
申请人： Priya Rajagopal , David M. Durham
发明人： Priya Rajagopal , David M. Durham
IPC分类号： G06F15/16
CPC分类号： G06F1/12
摘要： A method and apparatus are provided that allow processing engines to be synchronized to each other with high accuracy. In one embodiment, the invention includes obtaining a processor tick counter value from a first processing engine, comparing the obtained processor tick counter value to a processor tick counter value from a second processing engine and determining a timing offset for synchronizing the first processing engine and the second processing engine using the comparison. The invention may further include obtaining a processor tick counter value by sending a request message from the second processing engine to the first processing engine, and receiving a reply from the first processing engine at the second processing engine. The processor tick counter value at the second processing engine can be determined by recording the time at which the request message is sent and by recording the time at which the reply is received. The invention can further include obtaining a processor frequency from the first processing engine, obtaining a processor frequency from the second processing engine and correcting the timing offset for any difference between the first processing engine frequency and the second processing engine frequency.
摘要翻译：提供了一种方法和装置，其允许处理引擎以高精度彼此同步。在一个实施例中，本发明包括从第一处理引擎获得处理器刻度计数器值，将得到的处理器刻度计数值与来自第二处理引擎的处理器刻度计数器值进行比较，并确定用于使第一处理引擎和第二处理引擎使用比较。本发明还可以包括通过从第二处理引擎向第一处理引擎发送请求消息并且在第二处理引擎处接收来自第一处理引擎的回复来获得处理器计数值。可以通过记录发送请求消息的时间并记录回复的时间来确定第二处理引擎处理器计数器值。本发明还可以包括从第一处理引擎获得处理器频率，从第二处理引擎获得处理器频率，并且校正第一处理引擎频率和第二处理引擎频率之间的差异的定时偏移。

69. 发明申请

US20220014356A1 SEAMLESS ACCESS TO TRUSTED DOMAIN PROTECTED MEMORY BY VIRTUAL MACHINE MANAGER USING TRANSFORMER KEY IDENTIFIER 有权
公开(公告)号：US20220014356A1
公开(公告)日：2022-01-13
申请号：US17485146
申请日：2021-09-24
申请人： David M. Durham , Siddhartha Chhabra
发明人： David M. Durham , Siddhartha Chhabra
IPC分类号： H04L9/08 , G06F9/455
摘要： In one embodiment, an apparatus includes a processor comprising at least one core to execute instructions of a plurality of virtual machines (VMs) and a virtual machine monitor (VMM), and a cryptographic engine to protect data associated with the plurality of VMs through use of a plurality of private keys and a trusted transformer key, where each of the plurality of private keys are to protect program instructions and data of a respective VM and the trusted transformer key is to protect management structure data for the plurality of VMs. The processor is further to provide, to the VMM, read and write access to the management structure data through an untrusted transformer key

70. 发明申请

US20170185529A1 Techniques for Data storage protection and integrity checking 审中-公开
公开(公告)号：US20170185529A1
公开(公告)日：2017-06-29
申请号：US14998323
申请日：2015-12-24
申请人： Siddhartha Chhabra , David M. Durham
发明人： Siddhartha Chhabra , David M. Durham
IPC分类号： G06F12/14 , G06F12/08 , G06F3/06
CPC分类号： G06F3/0685 , G06F3/0623 , G06F3/0661 , G06F12/023 , G06F12/1408 , G06F12/145 , G06F21/602 , G06F21/82 , G06F2212/1052 , G06F2212/401 , G06F2212/402 , G06F2212/60
摘要： Various embodiments are generally directed to techniques for encrypting stored data. An apparatus includes a processor component comprising a cache that comprises a cache line to store a first block of data corresponding to a second block of encrypted data stored within a storage; a compressor to compress the data within the first block to generate compressed data within the first block to clear sufficient storage space within the first block to store metadata associated with generation of the second block of encrypted data from the first block in response to eviction of the first block from the cache line; and an encrypter to encrypt the compressed data within the first block to generate the encrypted data within the second block and to store encryption metadata associated with encrypting the compressed data within the second block as a portion of the metadata associated with the generation of the second block.

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