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61. 发明授权

US06645861B2 Self-aligned silicide process for silicon sidewall source and drain contacts 失效
标题翻译：用于硅侧壁源极和漏极触点的自对准硅化物工艺
公开(公告)号：US06645861B2
公开(公告)日：2003-11-11
申请号：US09836197
申请日：2001-04-18
申请人： Cyril Cabral, Jr. , Kevin K. Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Paul Michael Solomon , Ying Zhang
发明人： Cyril Cabral, Jr. , Kevin K. Chan , Guy Moshe Cohen , Kathryn Wilder Guarini , Christian Lavoie , Paul Michael Solomon , Ying Zhang
IPC分类号： H01L2144
CPC分类号： H01L29/6653 , H01L21/28052 , H01L21/28518 , H01L29/41783 , H01L29/456 , H01L29/66507 , H01L29/66772 , H01L29/78618 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.
摘要翻译：在具有含硅区域的受控消耗的非平面含硅区域上形成金属硅化物接触的方法（以及由此形成的结构）包括在含硅区域上形成覆盖金属层，在金属上形成硅层层，相对于金属的硅层各向异性地选择性地蚀刻，在第一温度下使金属与硅反应以形成金属硅合金，蚀刻金属层的未反应部分，在第二温度退火以形成金属合金 -Si2，并且选择性地蚀刻未反应的硅层。

62. 发明授权

US08889537B2 Implantless dopant segregation for silicide contacts 有权
标题翻译：用于硅化物接触的无植入物掺杂剂分离
公开(公告)号：US08889537B2
公开(公告)日：2014-11-18
申请号：US12833272
申请日：2010-07-09
申请人： Cryil Cabral, Jr. , John M. Cotte , Dinesh R. Koli , Laura L. Kosbar , Mahadevaiyer Krishnan , Christian Lavoie , Stephen M. Rossnagel , Zhen Zhang
发明人： Cryil Cabral, Jr. , John M. Cotte , Dinesh R. Koli , Laura L. Kosbar , Mahadevaiyer Krishnan , Christian Lavoie , Stephen M. Rossnagel , Zhen Zhang
IPC分类号： H01L21/28 , H01L21/285 , H01L29/45
CPC分类号： H01L21/28512 , H01L21/28518 , H01L29/456
摘要： A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.
摘要翻译：在半导体材料和硅化物层之间的结处形成分离的界面掺杂剂层的方法包括在半导体材料上沉积掺杂的金属层; 退火所述掺杂金属层和所述半导体材料，其中所述退火使所述掺杂金属层的一部分和所述半导体材料的一部分反应以在所述半导体材料上形成所述硅化物层，并且其中所述退火还导致所述分离的界面掺杂剂层，以形成在半导体材料和硅化物层之间，分离的界面掺杂剂层包含来自掺杂金属层的掺杂剂; 以及从所述硅化物层去除所述掺杂金属层的未反应部分。

63. 发明申请

US20070254479A1 Method for forming self-aligned metal silicide contacts 有权
标题翻译：用于形成自对准金属硅化物接触的方法
公开(公告)号：US20070254479A1
公开(公告)日：2007-11-01
申请号：US11415922
申请日：2006-05-01
申请人： Sunfei Fang , Randolph Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Renee Mo , Balasubramanian Pranatharthiharan , Jay Strane
发明人： Sunfei Fang , Randolph Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Renee Mo , Balasubramanian Pranatharthiharan , Jay Strane
IPC分类号： H01L21/44 , H01L21/302
CPC分类号： H01L21/28518 , C23F1/28 , C23F1/30 , C23F1/44
摘要： The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.
摘要翻译：本发明涉及一种用于在由暴露的电介质区彼此间隔开的至少两个含硅半导体区域上形成自对准金属硅化物接触的方法。优选地，如此形成的每个自对准金属硅化物触点至少包括具有基本平滑表面的至少硅化镍和铂硅化物，并且暴露的电介质区域基本上不含金属和金属硅化物。更优选地，该方法包括镍或镍合金沉积，低温退火，镍蚀刻，高温退火和王水腐蚀的步骤。

64. 发明申请

US20060051961A1 Method and process for forming a self-aligned silicide contact 有权
标题翻译：用于形成自对准硅化物接触的方法和工艺
公开(公告)号：US20060051961A1
公开(公告)日：2006-03-09
申请号：US10935497
申请日：2004-09-07
申请人： Cyril Cabral , Michael Cobb , Balasubramanian Pranatharthi Haran , Randolph Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Andrew Mansson , Horatio Wildman
发明人： Cyril Cabral , Michael Cobb , Balasubramanian Pranatharthi Haran , Randolph Knarr , Mahadevaiyer Krishnan , Christian Lavoie , Andrew Mansson , Horatio Wildman
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665
摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step. A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.
摘要翻译：本发明提供一种形成自对准Ni合金硅化物接触的方法。本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金，整个半导体结构，其包括至少一个栅极堆叠区域。包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。与诸如SiO 2和Si 3 N 4 N之类的绝缘材料直接接触的金属在金属合金硅化物接触期间不会转化为金属合金硅化物接触退火步骤。然后执行选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属。

65. 发明授权

US07759208B1 Low temperature ion implantation for improved silicide contacts 失效
标题翻译：低温离子注入用于改善硅化物接触
公开(公告)号：US07759208B1
公开(公告)日：2010-07-20
申请号：US12412406
申请日：2009-03-27
申请人： Asa Frye , Christian Lavoie , Ahmet S. Ozcan , Donald R. Wall
发明人： Asa Frye , Christian Lavoie , Ahmet S. Ozcan , Donald R. Wall
IPC分类号： H01L21/36
CPC分类号： H01L21/265 , H01L21/28518 , H01L29/665 , H01L29/78
摘要： Embodiments of the present invention provide a method that cools a substrate to a temperature below 10° C. and then implants ions into the substrate while the temperature of the substrate is below 10° C. The implanting causes damage to a first depth of the substrate to create an amorphized region in the substrate. The method forms a layer of metal on the substrate and heats the substrate until the metal reacts with the substrate and forms a silicide region within the amorphized region of the substrate. The depth of the silicide region is at least as deep as the first depth.
摘要翻译：本发明的实施方案提供了一种将基材冷却至低于10℃的温度，然后在基材的温度低于10℃时将离子注入基底中的方法。植入会导致基底的第一深度的损伤以在基底中产生非晶化区域。该方法在衬底上形成金属层并加热衬底，直到金属与衬底反应并在衬底的非晶化区域内形成硅化物区域。硅化物区域的深度至少与第一深度一样深。

66. 发明授权

US08927422B2 Raised silicide contact 有权
标题翻译：引起硅化物接触
公开(公告)号：US08927422B2
公开(公告)日：2015-01-06
申请号：US13525401
申请日：2012-06-18
申请人： Emre Alptekin , Nathaniel Berliner , Christian Lavoie , Kam-Leung Lee , Ahmet Serkan Ozcan
发明人： Emre Alptekin , Nathaniel Berliner , Christian Lavoie , Kam-Leung Lee , Ahmet Serkan Ozcan
IPC分类号： H01L21/44 , H01L21/31 , H01L21/285 , H01L29/66 , H01L21/02 , H01L21/8238
CPC分类号： H01L21/28518 , H01L21/02063 , H01L21/28525 , H01L21/76814 , H01L21/823814 , H01L23/485 , H01L29/665 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a raised silicide contact including depositing a layer of silicon at a bottom of a contract trench using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide, a width of the silicide and the contact trench are substantially equal; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° C. in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.
摘要翻译：一种用于形成高硅化物接触的方法，包括使用气体簇注入技术在合同沟槽的底部沉积硅层，所述气体簇注入技术加速硅原子簇，导致它们穿过硅化物顶表面上的表面氧化物，宽度的硅化物和接触沟槽基本相等; 将包含硅层的硅化物在惰性气氛中加热至约300℃至约950℃的温度，使来自硅层的硅与部分形成在含硅衬底中的剩余硅化物反应; 以及从所述硅层形成凸起的硅化物，其中所述凸起的硅化物的厚度大于所述硅化物的厚度，并且所述硅化物在所述含硅衬底的顶表面上方突出。

67. 发明授权

US08895379B2 Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same 有权
标题翻译：集成电路具有具有降低的硅化物接触电阻的升高的源极漏极器件和用于制造它们的方法
公开(公告)号：US08895379B2
公开(公告)日：2014-11-25
申请号：US13344806
申请日：2012-01-06
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Christian Lavoie
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Christian Lavoie
IPC分类号： H01L21/336
CPC分类号： H01L29/66515 , H01L21/28518 , H01L21/76805 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L23/485 , H01L27/0883 , H01L27/1052 , H01L27/1203 , H01L29/0847 , H01L29/41766 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/78 , H01L29/7843 , H01L29/7845 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： A structure has at least one field effect transistor having a gate stack disposed between raised source drain structures that are adjacent to the gate stack. The gate stack and raised source drain structures are disposed on a surface of a semiconductor material. The structure further includes a layer of field dielectric overlying the gate stack and raised source drain structures and first contact metal and second contact metal extending through the layer of field dielectric. The first contact metal terminates in a first trench formed through a top surface of a first raised source drain structure, and the second contact metal terminates in a second trench formed through a top surface of a second raised source drain structure. Each trench has silicide formed on sidewalls and a bottom surface of at least a portion of the trench. Methods to fabricate the structure are also disclosed.
摘要翻译：结构具有至少一个场效应晶体管，其栅极堆叠设置在与栅极堆叠相邻的凸起的源极漏极结构之间。栅极堆叠和升高的源极漏极结构设置在半导体材料的表面上。该结构还包括覆盖栅极叠层和升高的源极漏极结构的场介电层，以及延伸穿过场电介质层的第一接触金属和第二接触金属。第一接触金属终止在通过第一凸起源极漏极结构的顶表面形成的第一沟槽中，并且第二接触金属终止于通过第二凸起源极漏极结构的顶表面形成的第二沟槽中。每个沟槽具有形成在沟槽的至少一部分的侧壁和底表面上的硅化物。还公开了制造该结构的方法。

68. 发明授权

US08859316B2 Schottky junction si nanowire field-effect bio-sensor/molecule detector 有权
标题翻译：肖特基结si纳米线场效应生物传感器/分子检测器
公开(公告)号：US08859316B2
公开(公告)日：2014-10-14
申请号：US12825527
申请日：2010-06-29
申请人： Dechao Guo , Christian Lavoie , Christine Ouyang Qiqing , Yanning Sun , Zhen Zhang
发明人： Dechao Guo , Christian Lavoie , Christine Ouyang Qiqing , Yanning Sun , Zhen Zhang
IPC分类号： H01L21/00 , H01L29/06 , G01N27/414
CPC分类号： G01N27/4145 , G01N27/4146 , H01L29/0673
摘要： A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule.
摘要翻译：肖特基结的硅纳米线场效应生物传感器/分子检测器，纳米线厚度为10纳米或更小，并具有对准的源极/漏极功能，以提高灵敏度。纳米线通道涂覆有目标分子吸收的表面处理，其可以充分调节肖特基结之间的通道的电导率以定性和定量地测量分子的存在和量。

69. 发明授权

US08741753B2 Use of band edge gate metals as source drain contacts 有权
标题翻译：使用带边栅极金属作为源极漏极触点
公开(公告)号：US08741753B2
公开(公告)日：2014-06-03
申请号：US13611736
申请日：2012-09-12
申请人： Kisik Choi , Christian Lavoie , Paul M. Solomon , Bin Yang , Zhen Zhang
发明人： Kisik Choi , Christian Lavoie , Paul M. Solomon , Bin Yang , Zhen Zhang
IPC分类号： H01L21/20 , H01L21/3205 , H01L21/00
CPC分类号： H01L29/7833 , H01L21/28512 , H01L29/4958 , H01L29/4966 , H01L29/66545
摘要： A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.
摘要翻译：一种器件包括形成在半导体衬底中的沟道上方的栅叠层。栅极堆叠包括栅极绝缘体材料层，覆盖栅极绝缘体材料层的栅极金属层和覆盖层带边缘栅极金属的接触金属层。该装置还包括邻近通道的源极和漏极接触。源极和漏极触点各自包括覆盖并与半导体衬底的掺杂区域直接电接触的栅极金属层以及覆盖在栅极金属层上的接触金属层。

70. 发明申请

US20140073130A1 FORMING NICKEL-PLATINUM ALLOY SELF-ALIGNED SILICIDE CONTACTS 有权
标题翻译：形成镍 - 铂合金自对准硅化物接触
公开(公告)号：US20140073130A1
公开(公告)日：2014-03-13
申请号：US13613579
申请日：2012-09-13
申请人： David F. Hilscher , Christian Lavoie , Ahmet S. Ozcan
发明人： David F. Hilscher , Christian Lavoie , Ahmet S. Ozcan
IPC分类号： H01L21/3205
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： A method of performing a silicide contact process comprises a forming a nickel-platinum alloy (NiPt) layer over a semiconductor device structure; performing a first rapid thermal anneal (RTA) so as to react portions of the NiPt layer in contact with semiconductor regions of the semiconductor device structure, thereby forming metal rich silicide regions; performing a first wet etch to remove at least a nickel constituent of unreacted portions of the NiPt layer; performing a second wet etch using a dilute Aqua Regia treatment comprising nitric acid (HNO3), hydrochloric acid (HCl) and water (H2O) to remove any residual platinum material from the unreacted portions of the NiPt layer; and following the dilute Aqua Regia treatment, performing a second RTA to form final silicide contact regions from the metal rich silicide regions.
摘要翻译：执行硅化物接触工艺的方法包括在半导体器件结构上形成镍 - 铂合金（NiPt）层; 执行第一快速热退火（RTA），以使NiPt层的与半导体器件结构的半导体区域接触的部分反应，由此形成富金属硅化物区域; 执行第一湿蚀刻以去除至少NiPt层的未反应部分的镍组分; 使用包含硝酸（HNO 3），盐酸（HCl）和水（H 2 O）的稀释Aqua Regia处理进行第二次湿蚀刻以从NiPt层的未反应部分去除任何残余的铂材料; 并且在稀释的Aqua Regia处理之后，执行第二个RTA从富金属硅化物区形成最终的硅化物接触区。

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