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61. 发明申请

US20110164461A1 Memory Device 有权
标题翻译：存储设备
公开(公告)号：US20110164461A1
公开(公告)日：2011-07-07
申请号：US13050142
申请日：2011-03-17
申请人： Chung-Kuang Chen , Yi-Te Shih , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Yi-Te Shih , Chun-Hsiung Hung
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C8/12 , G11C7/1006 , G11C7/1012 , G11C2207/002 , G11C2207/005
摘要： A memory device comprises first memory block having first boundary cell and second memory block having second boundary cell. Data of the first and the second boundary cells are outputted simultaneously corresponding to a plurality of column selection signals.
摘要翻译：存储器件包括具有第一边界单元的第一存储器块和具有第二边界单元的第二存储器块。与多个列选择信号同时输出第一和第二边界单元的数据。

62. 发明申请

US20110157986A1 MEMORY AND OPERATING METHOD THEREOF 有权
标题翻译：其记忆和操作方法
公开(公告)号：US20110157986A1
公开(公告)日：2011-06-30
申请号：US13041642
申请日：2011-03-07
申请人： CHUNG-KUANG CHEN , Han-Sung Chen , Chun-Hsiung Hung
发明人： CHUNG-KUANG CHEN , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C16/06
CPC分类号： G11C29/02 , G11C8/08 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： A memory and an operating method thereof are provided therein. When searching a boundary of a threshold voltage distribution of the memory, data errors resulted from tail bits of the memory would be corrected. Therefore, a sensing window could be broader, and the boundary of the threshold voltage distribution could be determined precisely.
摘要翻译：在其中提供存储器及其操作方法。当搜索存储器的阈值电压分布的边界时，将校正由存储器的尾部位产生的数据错误。因此，感测窗口可以更宽，并且可以精确地确定阈值电压分布的边界。

63. 发明申请

US20110128809A1 Method and Apparatus of Addressing A Memory Integrated Circuit 有权
标题翻译：寻址存储器集成电路的方法和装置
公开(公告)号：US20110128809A1
公开(公告)日：2011-06-02
申请号：US12769456
申请日：2010-04-28
申请人： Chun-Hsiung Hung , Kuen-Long Chang , Hsieh-Ming Chih
发明人： Chun-Hsiung Hung , Kuen-Long Chang , Hsieh-Ming Chih
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/12
摘要： A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.
摘要翻译：存储器集成电路具有访问存储器集成电路的存储单元的控制电路。控制电路响应于包括第一命令和第二命令的命令。第一个命令指定高位地址位集合。第二个命令指定低位地址位集合。地址位的高位集合和地址位的低位集合构成存储器集成电路的完整访问地址。第一个命令和第二个命令在命令代码中有所不同。

64. 发明申请

US20110128791A1 Method and Apparatus of Performing an Erase Operation on a Memory Integrated Circuit 有权
标题翻译：在存储器集成电路上执行擦除操作的方法和装置
公开(公告)号：US20110128791A1
公开(公告)日：2011-06-02
申请号：US12834686
申请日：2010-07-12
申请人： Yi-Fan Chang , Cheng Ming Yih , Su-chueh Lo , Jian Shing Liu , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Yi-Fan Chang , Cheng Ming Yih , Su-chueh Lo , Jian Shing Liu , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C16/06 , G11C16/16
CPC分类号： G11C16/14 , G11C16/344 , G11C16/3477
摘要： Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines.
摘要翻译：各种讨论的方法包括在擦除验证和擦除擦除操作的子操作期间改进擦除组的边缘字线和中心字线的分组。在另一种方法中，改变边缘字线的电压电平以解决擦除组的过擦除问题，并且还提高擦除时间性能。另一种方法使用虚拟字线。

65. 发明申请

US20110085384A1 CURRENT SINK SYSTEM FOR SOURCE-SIDE SENSING 有权
标题翻译：用于源端感测的电流源系统
公开(公告)号：US20110085384A1
公开(公告)日：2011-04-14
申请号：US12833523
申请日：2010-07-09
申请人： CHUNG-KUANG CHEN , Han-Sung Chen , Chun-Hsiung Hung
发明人： CHUNG-KUANG CHEN , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C16/06
CPC分类号： G11C16/26 , G11C7/062 , G11C7/067 , G11C2207/063
摘要： Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of a reference current provided by a reference current source such as a reference cell.
摘要翻译：基于来自存储单元的源极端子的读取电流与从读出电流抽取的吸收电流之间的电流差，确定存储单元中存储的源极侧感测技术。吸收电流响应于由参考电流源（例如参考单元）提供的参考电流的大小来绘制。

66. 发明申请

US20110085380A1 Method of Programming a Memory 有权
标题翻译：存储器编程方法
公开(公告)号：US20110085380A1
公开(公告)日：2011-04-14
申请号：US12970222
申请日：2010-12-16
申请人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C16/10 , G11C16/04 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an nth phase are programmed into the targeted multi-level cells. Data corresponding to an (n+1)th phase is modified to make the data corresponding to the (n+1)th phase be the same as the data corresponding to the nth phase if the targeted multi-level cells pass a programming verification process according to an nth programming verification voltage. The above steps are repeated until n is equal to a maximum, n being a positive integer.
摘要翻译：一种对存储器进行编程的方法，其中所述存储器包括具有多个多电平单元的许多存储区域。每个存储器区域包括第一位线，第二位线，数据缓冲器和保护单元。耦合到第一和第二位线的保护单元和数据缓冲器防止编程错误发生。在编程方法的实施例中，对应的数据分别输入到数据缓冲器。对应于第n阶段的数据被编程到目标多级单元中。修改对应于第（n + 1）个相位的数据，以使对应于第（n + 1）相的数据与对应于第n相的数据相同，如果目标多电平单元通过编程验证处理根据第n个编程验证电压。重复上述步骤直到n等于最大值，n为正整数。

67. 发明授权

US07924614B2 Memory and boundary searching method thereof 有权
标题翻译：其内存及边界搜索方法
公开(公告)号：US07924614B2
公开(公告)日：2011-04-12
申请号：US12355962
申请日：2009-01-19
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C16/04
CPC分类号： G11C29/02 , G11C8/08 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： A memory and a boundary searching method thereof are provided therein. When searching a boundary of a threshold voltage distribution of the memory, data errors resulted from tail bits of the memory would be corrected. Therefore, a sensing window could be broader, and the boundary of the threshold voltage distribution could be determined precisely.
摘要翻译：其中提供了一种存储器及其边界搜索方法。当搜索存储器的阈值电压分布的边界时，将校正由存储器的尾部位产生的数据错误。因此，感测窗口可以更宽，并且可以精确地确定阈值电压分布的边界。

68. 发明授权

US07903498B2 Y-decoder and decoding method thereof 有权
标题翻译： Y解码器及其解码方法
公开(公告)号：US07903498B2
公开(公告)日：2011-03-08
申请号：US12205279
申请日：2008-09-05
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： A Y-decoder includes a selection unit and a Y-MUX. The selection unit is coupled to the memory array for selecting the column lines. The Y-MUX is coupled to the selection unit for supplying a voltage to the selected column line. The Y-MUX includes a first switch, a second switch, a third switch and a fourth switch coupled in parallel. The first switch and the second switch are respectively for receiving a first shielding voltage and a second shielding voltage. The third switch and the fourth switch are respectively for receiving a first sensing voltage and a second sensing voltage.
摘要翻译： Y解码器包括选择单元和Y-MUX。选择单元耦合到用于选择列线的存储器阵列。 Y-MUX耦合到选择单元，用于向所选择的列线提供电压。 Y-MUX包括并联耦合的第一开关，第二开关，第三开关和第四开关。第一开关和第二开关分别用于接收第一屏蔽电压和第二屏蔽电压。第三开关和第四开关分别用于接收第一感测电压和第二感测电压。

69. 发明申请

US20110016291A1 Serial Memory Interface for Extended Address Space 有权
标题翻译：用于扩展地址空间的串行存储器接口
公开(公告)号：US20110016291A1
公开(公告)日：2011-01-20
申请号：US12813395
申请日：2010-06-10
申请人： Yulan Kuo , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Yulan Kuo , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G06F12/06
CPC分类号： G06F9/30076 , G06F9/30189 , G06F9/342
摘要： An integrated circuit memory device has a memory array and control logic with at least a first addressing mode in which the instruction includes a first instruction code and an address of a first length; and a second addressing mode in which the instruction includes the first instruction code and an address of a second length. The first length of the address is different from the second length of the address.
摘要翻译：集成电路存储器件具有存储器阵列和具有至少第一寻址模式的控制逻辑，其中指令包括第一指令代码和第一长度的地址; 以及第二寻址模式，其中指令包括第一指令代码和第二长度的地址。地址的第一个长度与地址的第二个长度不同。

70. 发明授权

US07773421B2 Method and apparatus for accessing memory with read error by changing comparison 有权
标题翻译：通过改变比较读取错误来访问存储器的方法和装置
公开(公告)号：US07773421B2
公开(公告)日：2010-08-10
申请号：US12275606
申请日：2008-11-21
申请人： Chun-Hsiung Hung , Han-Sung Chen
发明人： Chun-Hsiung Hung , Han-Sung Chen
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G06F11/1008 , G11C29/52 , G11C2029/0411
摘要： In response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command, the comparison process is changed, between i) a value representing accessed data and ii) a reference applied to such accesses to distinguish between logical levels. For example, the read bias arrangement and/or a read reference of a memory integrated circuit is changed.
摘要翻译：响应于先前产生的与先前编程的数据位相关联的检验代码与响应于读取命令生成的最近生成的检验代码之间的不一致，比较过程在i）表示访问数据的值和ii）参考这些访问来区分逻辑级别。例如，存储器集成电路的读取偏置布置和/或读取参考被改变。

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