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61. 发明申请

US20120274647A1 PIEZOELECTRIC RESONATORS AND FABRICATION PROCESSES 审中-公开
标题翻译：压电谐振器和制造工艺
公开(公告)号：US20120274647A1
公开(公告)日：2012-11-01
申请号：US13094687
申请日：2011-04-26
申请人： Je-Hsiung Lan , Sang-June Park , Jonghae Kim , Evgeni Gousev , Matthew Nowak , Philip J. Stephanou , Justin Black , Kurt Petersen , Srinivasan Ganapathi
发明人： Je-Hsiung Lan , Sang-June Park , Jonghae Kim , Evgeni Gousev , Matthew Nowak , Philip J. Stephanou , Justin Black , Kurt Petersen , Srinivasan Ganapathi
IPC分类号： H01L41/053 , G09G5/39 , H01L41/22 , G06T1/60
CPC分类号： H03H3/0072 , H03H9/2447 , Y10T29/42
摘要： This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, a sacrificial layer is deposited on an insulating substrate. A lower electrode layer is formed proximate the sacrificial layer. A piezoelectric layer is deposited on the lower electrode layer. An upper electrode layer is formed on the piezoelectric layer. At least a portion of the sacrificial layer is removed to define a cavity such that at least a portion of the lower electrode layer is spaced apart from the insulating substrate.
摘要翻译：本公开提供了机电系统谐振器结构，设备，装置，系统和相关过程的实现。在一个方面，牺牲层沉积在绝缘衬底上。在牺牲层附近形成下电极层。压电层沉积在下电极层上。在压电层上形成上电极层。去除牺牲层的至少一部分以限定空腔，使得下电极层的至少一部分与绝缘基板间隔开。

62. 发明申请

US20120056680A1 Three Dimensional Inductor, Transformer and Radio Frequency Amplifier 有权
标题翻译：三维电感，变压器和射频放大器
公开(公告)号：US20120056680A1
公开(公告)日：2012-03-08
申请号：US13294351
申请日：2011-11-11
申请人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Lew G. Chua-Eoan , Seyfollah S. Bazarjani , Matthew Nowak
发明人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Lew G. Chua-Eoan , Seyfollah S. Bazarjani , Matthew Nowak
IPC分类号： H03F3/16
CPC分类号： H01L28/10 , H01F17/0013 , H01F19/04 , H01F2017/002 , H01L23/481 , H01L23/5227 , H01L27/0207 , H01L2224/16145 , H01L2924/3011
摘要： A three dimensional on-chip radio frequency amplifier is disclosed that includes first and second transformers and a first transistor. The first transformer includes first and second inductively coupled inductors. The second transformer includes third and fourth inductively coupled inductors. Each inductor includes multiple first segments in a first metal layer; multiple second segments in a second metal layer; first and second inputs, and multiple through vias coupling the first and second segments to form a continuous path between the first and second inputs. The first input of the first inductor is coupled to an amplifier input; the first input of the second inductor is coupled to the first transistor gate; the first input of the third inductor is coupled to the first transistor drain, the first input of the fourth inductor is coupled to an amplifier output. The second inductor inputs and the first transistor source are coupled to ground.
摘要翻译：公开了一种三维片上射频放大器，其包括第一和第二变压器和第一晶体管。第一变压器包括第一和第二电感耦合电感器。第二变压器包括第三和第四电感耦合电感器。每个电感器包括在第一金属层中的多个第一段; 第二金属层中的多个第二段; 第一和第二输入以及耦合第一和第二段的多通孔，以形成第一和第二输入之间的连续路径。第一电感器的第一输入耦合到放大器输入端; 第二电感器的第一输入耦合到第一晶体管栅极; 第三电感器的第一输入耦合到第一晶体管漏极，第四电感器的第一输入耦合到放大器输出端。第二电感器输入和第一晶体管源耦合到地。

63. 发明授权

US08067816B2 Techniques for placement of active and passive devices within a chip 有权
标题翻译：有源和无源器件放置在芯片内的技术
公开(公告)号：US08067816B2
公开(公告)日：2011-11-29
申请号：US12364844
申请日：2009-02-03
申请人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
发明人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
IPC分类号： H01L29/00
CPC分类号： H01L27/0617 , H01L23/481 , H01L23/5223 , H01L23/5227 , H01L27/0688 , H01L28/10 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).
摘要翻译：半导体管芯包括具有第一和第二侧面的半导体衬底层，与半导体衬底层的第二侧相邻的金属层，在半导体衬底层的第一侧上的有源层中的一个或多个有源器件; 以及与有源层电连通的金属层中的无源器件。无源器件可以通过硅通孔（TSV）电耦合到有源层。

64. 发明授权

US08041772B2 Autonomic sensor network ecosystem 有权
标题翻译：自主传感器网络生态系统
公开(公告)号：US08041772B2
公开(公告)日：2011-10-18
申请号：US11220961
申请日：2005-09-07
申请人： Riz S. Amanuddin , Jonghae Kim , Moon J. Kim , Eric C. Yee
发明人： Riz S. Amanuddin , Jonghae Kim , Moon J. Kim , Eric C. Yee
IPC分类号： G06F15/16 , G06F15/173
CPC分类号： H04W84/18 , H04L43/0817 , H04L67/104 , H04L67/1046 , H04L67/1059 , H04L67/1068 , H04L67/1093 , H04L67/12 , H04W24/00 , H04W72/04 , H04W74/06 , H04W88/16
摘要： The present invention provides a method, system and program product for deploying and allocating resources, and addressing threats in an autonomic sensor network ecosystem. Specifically, under the present invention, the autonomic sensor network ecosystem includes a set (e.g., one or more) of sensor networks each having a set of sensor peers and at least one super peer; a set of micro grid gateways; and a set of enterprise gateways. Each micro grid gateway is typically adapted to receive requests from a sensor network, an enterprise gateway, and/or another micro grid gateway. Moreover, each micro grid gateway includes a request broker for receiving the requests; a request queue manager for queuing the requests; a scheduler for scheduling the requests; and a resource manager for monitoring the set of sensor networks.
摘要翻译：本发明提供了用于部署和分配资源以及解决自主传感器网络生态系统中的威胁的方法，系统和程序产品。具体地说，在本发明的范围内，自主传感器网络生态系统包括一组（例如一个或多个）传感器网络，每个传感器网络具有一组传感器对等体和至少一个超级对等体; 一套微网格网关; 和一套企业网关。每个微网格网关通常适于接收来自传感器网络，企业网关和/或另一微网格网关的请求。此外，每个微网格网关包括用于接收请求的请求代理; 用于排队请求的请求队列管理器; 调度器，用于调度请求; 以及用于监测传感器网络集合的资源管理器。

65. 发明申请

US20110233718A1 Heterogeneous Technology Integration 审中-公开
标题翻译：异构技术集成
公开(公告)号：US20110233718A1
公开(公告)日：2011-09-29
申请号：US12731520
申请日：2010-03-25
申请人： Jonghae Kim , Evgeni P. Gousev , Matthew Michael Nowak
发明人： Jonghae Kim , Evgeni P. Gousev , Matthew Michael Nowak
IPC分类号： H01L23/52 , H01L23/488 , H01L23/48 , H01L21/70 , H01L23/49
CPC分类号： H01L25/0655 , H01L24/73 , H01L24/92 , H01L25/18 , H01L29/0657 , H01L2224/16105 , H01L2224/16137 , H01L2224/16195 , H01L2224/16227 , H01L2224/17181 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/73207 , H01L2224/73257 , H01L2224/92227 , H01L2924/10155 , H01L2924/10253 , H01L2924/00 , H01L2924/00014
摘要： A heterogeneous integrated circuit having at least one tier made of multiple technologies and a method of making the heterogeneous integrated circuit. The heterogeneous integrated circuit includes a package substrate, a first die of a first technology, and a second die of a second technology, where the two dies are located in the same tier. One die can surround the other die. The heterogeneous integrated circuit can also include a wire-bond and/or horizontal micro-bump coupling the two dies. The heterogeneous integrated circuit can also include a wire bond or vertical micro-bump coupling one of the dies to the package substrate. The vertical micro-bump coupling can include a through-via. The two technologies can be any of various technologies including CMOS, glass, sapphire and quartz. One die can also be adjacent to the other die on the same tier and the two dies coupled using a horizontal micro-bump.
摘要翻译：具有由多种技术制成的至少一层的异质集成电路和制造异质集成电路的方法。异质集成电路包括封装衬底，第一技术的第一裸片和第二技术的第二裸片，其中两个裸片位于同一层。一个模具可以围绕另一个模具。异质集成电路还可以包括耦合两个管芯的引线接合和/或水平微凸块。异质集成电路还可以包括引线接合或将一个管芯耦合到封装衬底的垂直微突起。垂直微凸块耦合可以包括通孔。这两种技术可以是包括CMOS，玻璃，蓝宝石和石英在内的各种技术。一个管芯也可以在同一层上与另一个管芯相邻，并且两个管芯使用水平微型焊盘进行耦合。

66. 发明申请

US20110087846A1 Accessing a Multi-Channel Memory System Having Non-Uniform Page Sizes 有权
标题翻译：访问具有不一致页面大小的多通道内存系统
公开(公告)号：US20110087846A1
公开(公告)日：2011-04-14
申请号：US12576693
申请日：2009-10-09
申请人： Feng Wang , Matthew Michael Nowak , Jonghae Kim
发明人： Feng Wang , Matthew Michael Nowak , Jonghae Kim
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , Y02D10/14
摘要： A method includes predicting a memory access pattern of each master of a plurality of masters. The plurality of masters can access a multi-channel memory via a crossbar interconnect, where the multi-channel memory has a plurality of banks The method includes identifying a page size associated with each bank of the plurality of banks The method also includes assigning at least one bank of the plurality of banks to each master of the plurality of masters based on the memory access pattern of each master.
摘要翻译：一种方法包括预测多个主机的每个主机的存储器访问模式。多个主器件可以经由跨通道互连访问多通道存储器，其中多通道存储器具有多个存储体。该方法包括识别与多个存储体中的每个存储体相关联的页面大小。该方法还包括至少分配基于每个主机的存储器访问模式，多个存储体中的一个存储体中的多个存储体的每一个存储模块。

67. 发明授权

US07912670B2 Testing processor cores 有权
标题翻译：测试处理器内核
公开(公告)号：US07912670B2
公开(公告)日：2011-03-22
申请号：US12128075
申请日：2008-05-28
申请人： Dae Ik Kim , Jonghae Kim , Moon J Kim , James R Moulic
发明人： Dae Ik Kim , Jonghae Kim , Moon J Kim , James R Moulic
IPC分类号： G01R31/00
CPC分类号： G06F11/24 , G01R31/3004 , G01R31/31721 , G01R31/318505
摘要： Systems, methods and program codes are provided for testing multi-core processor chip structures. Individual processor core power supply voltages are provided through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. In one example, a first power supply voltage supplied to a first processing core differs from a second core power supply voltage supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. Core power supply voltages may be selected from ordered discrete supply voltages derived by progressively raising or lowering a first supply voltage, optionally wherein the selected supply voltage also enables the core to operate within another performance specification.
摘要翻译：提供了系统，方法和程序代码，用于测试多核处理器芯片结构。单个处理器核心电源电压通过控制每个核心的单独电源来提供，在一个方面，以确保一个或多个核心以按照一个或多个性能规格的时钟速率运行。在一个示例中，提供给第一处理核心的第一电源电压与提供给第二处理核心的第二核心电源电压不同，两个核心都遵循参考时钟速率规范操作。核心电源电压可以从通过逐渐提高或降低第一电源电压而导出的有序离散电源电压中选择，任选地，其中所选择的电源电压还使得核能够在另一性能规格内操作。

68. 发明申请

US20110035529A1 Partitioning a Crossbar Interconnect in a Multi-Channel Memory System 有权
标题翻译：在多通道存储器系统中分隔交叉开关互连
公开(公告)号：US20110035529A1
公开(公告)日：2011-02-10
申请号：US12536991
申请日：2009-08-06
申请人： Feng Wang , Matthew Michael Nowak , Jonghae Kim
发明人： Feng Wang , Matthew Michael Nowak , Jonghae Kim
IPC分类号： G06F13/00
CPC分类号： G06F13/1663 , G06F13/1684 , Y02D10/14
摘要： A method includes identifying a first set of masters and a second set of masters from a plurality of masters. The plurality of masters have access to a multi-channel memory via a crossbar interconnect. The method includes partitioning the crossbar interconnect into a plurality of partitions comprising at least a first partition corresponding to the first set of masters and a second partition corresponding to the second set of masters. The method also includes allocating a first set of buffer areas within the multi-channel memory. The first set of buffer areas correspond to the first set of masters. The method further includes allocating a second set of buffer areas within the multi-channel memory. The second set of buffers correspond to the second set of masters.
摘要翻译：一种方法包括从多个主器件识别第一组主器件和第二组主器件。多个主机通过交叉开关互连访问多通道存储器。该方法包括将交叉开关互连划分成多个分区，其包括至少对应于第一组主机的第一分区和对应于第二组主机的第二分区。该方法还包括在多通道存储器内分配第一组缓冲区。第一组缓冲区对应于第一组主机。该方法还包括在多通道存储器内分配第二组缓冲区。第二组缓冲器对应于第二组主机。

69. 发明申请

US20110031586A1 High Breakdown Voltage Embedded MIM Capacitor Structure 有权
标题翻译：高击穿电压嵌入式MIM电容器结构
公开(公告)号：US20110031586A1
公开(公告)日：2011-02-10
申请号：US12536819
申请日：2009-08-06
申请人： Wootag Kang , Jonghae Kim
发明人： Wootag Kang , Jonghae Kim
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/40 , H01L27/0805 , H01L27/101
摘要： Methods and devices related to a plurality of high breakdown voltage embedded capacitors are presented. A semiconductor device may include gate material embedded in an insulator, a plurality of metal contacts, and a plurality of capacitors. The plurality of capacitors may include a lower electrode, a dielectric formed so as to cover a surface of the lower electrode, and an upper electrode formed on the dielectric. Further, the plurality of contacts may connect each of the lower electrodes of the plurality of capacitors to the gate material. The plurality of capacitors may be connected in series via the gate material.
摘要翻译：提出了与多个高击穿电压嵌入式电容器相关的方法和装置。半导体器件可以包括嵌入绝缘体中的栅极材料，多个金属触点和多个电容器。多个电容器可以包括下电极，形成为覆盖下电极的表面的电介质和形成在电介质上的上电极。此外，多个触点可以将多个电容器中的每个下电极连接到栅极材料。多个电容器可以经由栅极材料串联连接。

70. 发明申请

US20100193905A1 Techniques for Placement of Active and Passive Devices Within a Chip 有权
标题翻译：芯片内主动和被动设备放置技术
公开(公告)号：US20100193905A1
公开(公告)日：2010-08-05
申请号：US12364844
申请日：2009-02-03
申请人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
发明人： Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
IPC分类号： H01L27/08 , H01L21/98
CPC分类号： H01L27/0617 , H01L23/481 , H01L23/5223 , H01L23/5227 , H01L27/0688 , H01L28/10 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).
摘要翻译：半导体管芯包括具有第一和第二侧面的半导体衬底层，与半导体衬底层的第二侧相邻的金属层，在半导体衬底层的第一侧上的有源层中的一个或多个有源器件; 以及与有源层电连通的金属层中的无源器件。无源器件可以通过硅通孔（TSV）电耦合到有源层。

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