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61. 发明授权

US06803309B2 Method for depositing an adhesion/barrier layer to improve adhesion and contact resistance 失效
标题翻译：用于沉积粘合/阻挡层以提高粘附性和接触电阻的方法
公开(公告)号：US06803309B2
公开(公告)日：2004-10-12
申请号：US10190140
申请日：2002-07-03
申请人： Shih-Wei Chou , Chii-Ming Wu
发明人： Shih-Wei Chou , Chii-Ming Wu
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76802 , H01L21/76807 , H01L21/76814
摘要： A method for forming an adhesion/barrier liner with reduced fluorine contamination to improve adhesion and a specific contact resistance of metal interconnects including providing a semiconductor wafer having a process surface including an etched opening extending through a dielectric insulating layer thickness and in closed communication with a conductive underlayer surface; pre-heating the semiconductor wafer in a plasma reactor to a pre-heating temperature of at least about 400° C.; cleaning the etched opening according to a plasma assisted reactive pre-cleaning process (RPC) comprising nitrogen trifluoride (NF3); and, blanket depositing at least a first adhesion/barrier layer over the etched opening substantially free of fluorine containing residue.
摘要翻译：一种用于形成具有降低的氟污染物的粘合/阻挡衬里以提高金属互连的粘合性和特定接触电阻的方法，包括提供具有包括延伸穿过介电绝缘层厚度的蚀刻开口并与导电性密封连通的工艺表面的半导体晶片底层表面将等离子体反应器中的半导体晶片预热至至少约400℃的预热温度; 根据包括三氟化氮（NF 3）的等离子体辅助反应性预清洗工艺（RPC）清洁蚀刻开口; 并且在基本上不含氟残留物的蚀刻开口上至少铺设第一粘附/阻挡层。

62. 发明授权

US09881840B2 Method of fabricating gate electrode using a treated hard mask 有权
公开(公告)号：US09881840B2
公开(公告)日：2018-01-30
申请号：US13157179
申请日：2011-06-09
申请人： Yu-Lien Huang , Ziwei Fang , Tsan-Chun Wang , Chii-Ming Wu , Chun Hsiung Tsai
发明人： Yu-Lien Huang , Ziwei Fang , Tsan-Chun Wang , Chii-Ming Wu , Chun Hsiung Tsai
IPC分类号： H01L21/8238 , H01L21/3115 , H01L21/033 , H01L21/3213
CPC分类号： H01L21/823814 , H01L21/0337 , H01L21/31155 , H01L21/32139 , H01L21/823807
摘要： A hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided on the hard mask layer to transform the hard mask layer to be more resistant to wet etching solution. A patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.

63. 发明申请

US20120299121A1 Source/Drain Formation and Structure 有权
标题翻译：源/排水形成与结构
公开(公告)号：US20120299121A1
公开(公告)日：2012-11-29
申请号：US13114910
申请日：2011-05-24
申请人： Chii-Ming Wu , Chien-Chang Su , Hsien-Hsin Lin , Yi-Fang Pai
发明人： Chii-Ming Wu , Chien-Chang Su , Hsien-Hsin Lin , Yi-Fang Pai
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7834 , H01L21/2257 , H01L29/6659 , H01L29/66628 , H01L29/66636
摘要： A system and method for forming semiconductor structures is disclosed. An embodiment comprises forming a high diffusibility layer adjacent to a gate stack and forming a low diffusibility layer adjacent to the high diffusibility layer. After these two layers are formed, an anneal is performed to diffuse dopants from the high diffusibility layer underneath the gate stack to help form a channel region.
摘要翻译：公开了一种用于形成半导体结构的系统和方法。一个实施例包括形成与栅极堆叠相邻的高扩散层，并形成与高扩散层相邻的低扩散性层。在形成这两层之后，进行退火以从栅叠层下方的高扩散层扩散掺杂剂以帮助形成沟道区。

64. 发明授权

US08298925B2 Mechanisms for forming ultra shallow junction 有权
标题翻译：形成超浅结的机理
公开(公告)号：US08298925B2
公开(公告)日：2012-10-30
申请号：US12941509
申请日：2010-11-08
申请人： Chii-Ming Wu , Yu Lien Huang , Chun Hsiung Tsai
发明人： Chii-Ming Wu , Yu Lien Huang , Chun Hsiung Tsai
IPC分类号： H01L21/26 , H01L21/425 , H01L21/02
CPC分类号： H01L29/7831 , H01L21/2236 , H01L21/823418 , H01L21/823431 , H01L29/66795 , H01L29/66803
摘要： The embodiments of methods and structures are for doping fin structures by plasma doping processes to enable formation of shallow lightly doped source and drain (LDD) regions. The methods involve a two-step plasma doping process. The first step plasma process uses a heavy carrier gas, such as a carrier gas with an atomic weight equal to or greater than about 20 amu, to make the surfaces of fin structures amorphous and to reduce the dependence of doping rate on crystalline orientation. The second step plasma process uses a lighter carrier gas, which is lighter than the carrier gas for the first step plasma process, to drive the dopants deeper into the fin structures. The two-step plasma doping process produces uniform dopant profile beneath the outer surfaces of the fin structures.
摘要翻译：方法和结构的实施例用于通过等离子体掺杂工艺掺杂鳍结构，以形成浅掺杂的源极和漏极（LDD）区域。该方法涉及两步等离子体掺杂工艺。第一级等离子体工艺使用重载气，例如原子量等于或大于约20amu的载气，以使翅片结构的表面无定形并且降低掺杂速率对晶体取向的依赖性。第二级等离子体处理使用比用于第一级等离子体处理的载气轻的载气，以将掺杂剂更深地驱动到鳍结构中。两级等离子体掺杂工艺在翅片结构的外表面下方产生均匀的掺杂剂分布。

65. 发明授权

US06410424B1 Process flow to optimize profile of ultra small size photo resist free contact 有权
标题翻译：工艺流程优化超小尺寸光刻胶的自由接触
公开(公告)号：US06410424B1
公开(公告)日：2002-06-25
申请号：US09837599
申请日：2001-04-19
申请人： Ming-Huan Tsai , Chung-Long Chang , Chii-Ming Wu , Hun-Jan Tao
发明人： Ming-Huan Tsai , Chung-Long Chang , Chii-Ming Wu , Hun-Jan Tao
IPC分类号： H01L214763
CPC分类号： H01L21/76804 , H01L21/76802 , H01L21/76814 , H01L21/76829 , H01L21/76831 , Y10S438/975
摘要： A new processing sequence is provided for the creation of openings in layers of dielectric. Over a semiconductor surface are successively deposited an etch stop layer, a layer of dielectric and a hard mask layer. An opening is etched in the hard mask layer, the main opening is etched through the layer of dielectric and the etch stop layer. The surface is wet cleaned, after which a thin layer of silicon oxide is CVD deposited over the inside surfaces of the created opening. This thin layer of CVD oxide is subjected to argon sputter, providing of the critical dimensions of the upper region of the opening. Then the process continues with the deposition of the barrier metal, the filling of the opening with a conducting material to create the metal plug and the polishing of the surface of the deposited conducting material.
摘要翻译：提供了一种新的处理顺序，用于在电介质层中产生开口。在半导体表面上依次沉积蚀刻停止层，电介质层和硬掩模层。在硬掩模层中蚀刻开口，通过电介质层和蚀刻停止层蚀刻主开口。表面被湿清洗，之后在所产生的开口的内表面上CVD沉积薄层的氧化硅。对CVD氧化物薄层进行氩溅射，提供开口上部区域的临界尺寸。然后，该过程继续阻挡金属的沉积，用导电材料填充开口以产生金属塞和抛光沉积的导电材料的表面。

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