专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20130093097A1 Package-On-Package (PoP) Structure and Method 有权
标题翻译：封装封装（PoP）结构和方法
公开(公告)号：US20130093097A1
公开(公告)日：2013-04-18
申请号：US13271952
申请日：2011-10-12
申请人： Chen-Hua Yu , Chung-Shi Liu , Mirng-Ji Lii , Ming-Da Cheng , Chih-Wei Lin
发明人： Chen-Hua Yu , Chung-Shi Liu , Mirng-Ji Lii , Ming-Da Cheng , Chih-Wei Lin
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L25/50 , H01L21/31051 , H01L21/4846 , H01L21/4853 , H01L21/4857 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76802 , H01L21/76819 , H01L21/76877 , H01L21/76898 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5383 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L2221/68345 , H01L2224/04105 , H01L2224/12105 , H01L2224/13082 , H01L2224/131 , H01L2224/16225 , H01L2224/16237 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/73204 , H01L2224/73253 , H01L2224/73267 , H01L2224/81005 , H01L2224/81191 , H01L2224/81815 , H01L2224/83104 , H01L2225/06513 , H01L2225/06548 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H05K1/185 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2924/0665 , H01L2224/48
摘要： A package-on-package (PoP) structure comprises a first package and a second package. The first package comprises a first die, a second die, and a core material. The core material has a first surface and a second surface. A first redistribution layer (RDL) is on the first surface, and a second RDL is on the second surface. The first die is disposed in the core material between the first surface and the second surface. The second die is coupled to one of the first RDL and the second RDL. The second package comprises a third die and an interposer. The interposer has a first side and a second side. The third die is coupled to the second side of the interposer. The first package is coupled to the second package by first electrical connectors coupled to the second side of the interposer and the first RDL.
摘要翻译：封装封装（PoP）结构包括第一封装和第二封装。第一包装包括第一模具，第二模具和芯材料。芯材料具有第一表面和第二表面。第一再分配层（RDL）位于第一表面上，第二RDL位于第二表面上。第一模具设置在第一表面和第二表面之间的芯材料中。第二管芯耦合到第一RDL和第二RDL之一。第二包装包括第三管芯和插入件。插入器具有第一侧和第二侧。第三裸片耦合到插入器的第二侧。第一封装通过耦合到插入件的第二侧和第一RDL的第一电连接器耦合到第二封装。

62. 发明申请

US20120181669A1 FRAME CELL FOR SHOT LAYOUT FLEXIBILITY 有权
标题翻译：用于拍摄布局灵活性的框架单元
公开(公告)号：US20120181669A1
公开(公告)日：2012-07-19
申请号：US13409517
申请日：2012-03-01
申请人： Chin-Ming LIN , Chia-hung Huang , Chi-Ming Yang , Chin-Hsiang Lin , Yung-Cheng Chen , Chih-Wei Lin
发明人： Chin-Ming LIN , Chia-hung Huang , Chi-Ming Yang , Chin-Hsiang Lin , Yung-Cheng Chen , Chih-Wei Lin
IPC分类号： H01L23/544 , G06F17/50
CPC分类号： G03F7/70433
摘要： A method includes establishing an initial shot layout in which a number of shots are arranged in vertically aligned columns and horizontally aligned rows to cover a semiconductor wafer. At least one of a row of shots or a column of shots is shifted relative to an adjacent row or column of shots to establish at least one additional shot layout that differs from the initial shot layout in that shots in the at least one shifted row or column of shots are not aligned with the shots in the adjacent row or column of shots with which they were aligned in the initial shot layout. One of the initial shot layout and the at least one additional shot layout is selected as a final shot layout. The wafer is exposed to light using the final shot layout.
摘要翻译：一种方法包括建立初始照片布局，其中多个照片布置在垂直排列的列和水平排列的行中以覆盖半导体晶片。一排照片或一列照片中的至少一列相对于相邻的行或列发射位移，以建立与至少一个移位行中的拍摄中的初始镜头布局不同的至少一个附加镜头布局，或一列照片不与在初始镜头布局中对齐的相邻行或照片列中的镜头对齐。选择初始镜头布局和至少一个附加镜头布局之一作为最终镜头布局。使用最终镜头布局将晶片曝光。

63. 发明申请

US20110287628A1 Activation Treatments in Plating Processes 有权
标题翻译：电镀工艺中的活化处理
公开(公告)号：US20110287628A1
公开(公告)日：2011-11-24
申请号：US12784314
申请日：2010-05-20
申请人： Chih-Wei Lin , Ming-Da Cheng , Ming-Che Ho , Chung-Shi Liu
发明人： Chih-Wei Lin , Ming-Da Cheng , Ming-Che Ho , Chung-Shi Liu
IPC分类号： H01L21/445
CPC分类号： H01L21/288 , C25D7/123 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03831 , H01L2224/0401 , H01L2224/05166 , H01L2224/05181 , H01L2224/05572 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/11424 , H01L2224/11462 , H01L2224/11464 , H01L2224/11622 , H01L2224/1181 , H01L2224/11901 , H01L2224/1308 , H01L2224/13083 , H01L2224/13118 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/93 , H01L2924/00013 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2224/11 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552 , H01L2924/00 , H01L2224/1146
摘要： A method of forming a device includes performing a first plating process to form a first metallic feature, and performing an activation treatment to a surface of the first metallic feature in an activation treatment solution, wherein the activation treatment solution includes a treatment agent in de-ionized (DI) water. After the step of performing the activation treatment, performing a second plating process to form a second metallic feature and contacting the surface of the first metallic feature.
摘要翻译：一种形成装置的方法包括进行第一电镀工艺以形成第一金属特征，并且在活化处理溶液中对第一金属特征的表面进行活化处理，其中活化处理溶液包括处理剂，电离（DI）水。在执行激活处理的步骤之后，执行第二电镀处理以形成第二金属特征并接触第一金属特征的表面。

64. 发明授权

US07956375B2 Light emitting diode structure having a textured package lens 有权
标题翻译：具有纹理化封装透镜的发光二极管结构
公开(公告)号：US07956375B2
公开(公告)日：2011-06-07
申请号：US12485237
申请日：2009-06-16
申请人： Yueh-Han Li , Po-Tang Hsu , Chien-Ming Ko , Hung-Ching Lee , Chih-Wei Lin
发明人： Yueh-Han Li , Po-Tang Hsu , Chien-Ming Ko , Hung-Ching Lee , Chih-Wei Lin
IPC分类号： H01L29/22 , H01L29/227 , H01L33/00 , H01L31/0203
CPC分类号： H01L33/54 , H01L33/58
摘要： A light emitting diode structure and a light emitting diode structure forming method are provided. The light emitting diode structure includes a base, a diode chip, and a package lens. The diode chip is mounted on the base. The package lens covers the diode chip. The surface of the package lens includes a plurality of dot structures. The steps of the method include mounting a light-emitting diode chip on a base, assembling a package lens to cover the light emitting diodes chip, and forming a plurality of dot structures on the surface of the package lens.
摘要翻译：提供了发光二极管结构和发光二极管结构形成方法。发光二极管结构包括基座，二极管芯片和封装透镜。二极管芯片安装在基座上。封装透镜覆盖二极管芯片。封装透镜的表面包括多个点结构。该方法的步骤包括将发光二极管芯片安装在基座上，组装封装透镜以覆盖发光二极管芯片，以及在封装透镜的表面上形成多个点状结构。

65. 发明授权

US07883240B2 Light emitting diode based light source assembly 有权
标题翻译：基于发光二极管的光源组件
公开(公告)号：US07883240B2
公开(公告)日：2011-02-08
申请号：US11967034
申请日：2007-12-29
申请人： Pei-Chin Lee , Chih-Wei Lin , Hung-Kuang Hsu
发明人： Pei-Chin Lee , Chih-Wei Lin , Hung-Kuang Hsu
IPC分类号： F21S4/00
CPC分类号： F21V29/763 , F21K9/00 , F21V19/0055 , F21V29/004 , F21V29/74 , F21V29/89 , F21Y2115/10 , H01L2924/0002 , H01L2924/00
摘要： An LED based light source assembly (10) comprises a circuit board (11), a plurality of LEDs (13), a heat sink (15) and a plurality of fasteners (17). The circuit board comprises a first surface (12) and a second surface (14) opposite to the first surface. The first surface is provided with electrical conductive traces (118). The plurality of LEDs are arranged on the first surface of the circuit board and electrically connecting with the electrical wires of the circuit board. The heat sink thermally contacts the second surface of the circuit board. The plurality of fasteners each comprise a first end (172) and a second end (174) opposite to the first end. The first end of each of the fasteners abuts on the first surface of the circuit board. The second end of each of the fasteners extends through the circuit board to be secured to the heat sink.
摘要翻译：一种基于LED的光源组件（10）包括电路板（11），多个LED（13），散热片（15）和多个紧固件（17）。电路板包括与第一表面相对的第一表面（12）和第二表面（14）。第一表面设有导电迹线（118）。多个LED布置在电路板的第一表面上并与电路板的电线电连接。散热片与电路板的第二表面热接触。多个紧固件各自包括与第一端相对的第一端（172）和第二端（174）。每个紧固件的第一端邻接在电路板的第一表面上。每个紧固件的第二端延伸穿过电路板以固定到散热器。

66. 发明授权

US07876963B2 Symbol recognition method 有权
标题翻译：符号识别方法
公开(公告)号：US07876963B2
公开(公告)日：2011-01-25
申请号：US11846628
申请日：2007-08-29
申请人： Ming-Hung Lin , Chih-Wei Lin
发明人： Ming-Hung Lin , Chih-Wei Lin
IPC分类号： G06K9/48 , G06K9/62
CPC分类号： G06K9/2054 , G06K2209/01
摘要： A symbol recognition method for increasing the symbol recognition speed by the processor includes the steps of obtaining a pixel density value and an aspect ratio of the symbol image. Then, the center-point value and the corresponding radius value are obtained by a partitional clustering algorithm. In sequence, a pixel density value and the aspect ratio of the under recognized image are obtained, and compared with the values of the symbol image to determine whether the under recognized image is a single symbol image or not.
摘要翻译：用于通过处理器增加符号识别速度的符号识别方法包括以下步骤：获得符号图像的像素密度值和宽高比。然后，通过分数聚类算法获得中心点值和对应的半径值。顺序地，获得像素密度值和未识别图像的长宽比，并且与符号图像的值进行比较，以确定未识别的图像是否是单个符号图像。

67. 发明授权

US07655501B2 Wafer level package with good CTE performance 有权
标题翻译：晶圆级封装具有良好的CTE性能
公开(公告)号：US07655501B2
公开(公告)日：2010-02-02
申请号：US12141138
申请日：2008-06-18
申请人： Wen-Kun Yang , Tung-Chuan Wang , Chao-Nan Chou , Chih-Wei Lin
发明人： Wen-Kun Yang , Tung-Chuan Wang , Chao-Nan Chou , Chih-Wei Lin
IPC分类号： H01L21/00
CPC分类号： H01L23/3128 , H01L21/6835 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/82 , H01L24/97 , H01L2224/04105 , H01L2224/20 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01068 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/181 , H01L2924/19043 , H01L2924/351 , H01L2224/82 , H01L2924/00
摘要： The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the re-distribution built up layer. Terminal Conductive bumps are coupled to the UBM.
摘要翻译：本发明提供了一种包装结构，其包括具有预先形成的模具容纳空腔的基板和/或形成在基板的上表面内的端接触金属焊盘。通过粘合将模具设置在模具接收腔内，并且在模具和基板上形成介电层。在电介质层上形成至少一个重新分配建立层（RDL），并通过接触焊盘与芯片耦合。连接结构，例如UBM形成在重新分配建立的层上。端子导电凸块耦合到UBM。

68. 发明申请

US20080248614A1 WAFER LEVEL PACKAGE WITH GOOD CTE PERFORMANCE 有权
标题翻译：具有良好CTE性能的WAFER LEVEL PACKAGE
公开(公告)号：US20080248614A1
公开(公告)日：2008-10-09
申请号：US12141138
申请日：2008-06-18
申请人： Wen-Kun Yang , Tung-Chuan Wang , Chao-Nan Chou , Chih-Wei Lin
发明人： Wen-Kun Yang , Tung-Chuan Wang , Chao-Nan Chou , Chih-Wei Lin
IPC分类号： H01L21/58
CPC分类号： H01L23/3128 , H01L21/6835 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/82 , H01L24/97 , H01L2224/04105 , H01L2224/20 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01068 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/181 , H01L2924/19043 , H01L2924/351 , H01L2224/82 , H01L2924/00
摘要： The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the re-distribution built up layer. Terminal Conductive bumps are coupled to the UBM.
摘要翻译：本发明提供了一种包装结构，其包括具有预先形成的模具容纳空腔的基板和/或形成在基板的上表面内的端接触金属焊盘。通过粘合将模具设置在模具接收腔内，并且在模具和基板上形成介电层。在电介质层上形成至少一个重新分配建立层（RDL），并通过接触焊盘与芯片耦合。连接结构，例如UBM形成在重新分配建立的层上。端子导电凸块耦合到UBM。

69. 发明申请

US20080136004A1 MULTI-CHIP PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：多芯片包装结构及其形成方法
公开(公告)号：US20080136004A1
公开(公告)日：2008-06-12
申请号：US11608404
申请日：2006-12-08
申请人： Wen-Kun Yang , Chun-Hui Yu , Chao-Nan Chou , Chih-Wei Lin , Ching-Shun Huang
发明人： Wen-Kun Yang , Chun-Hui Yu , Chao-Nan Chou , Chih-Wei Lin , Ching-Shun Huang
IPC分类号： H01L23/488 , H01L21/56
CPC分类号： H01L24/97 , H01L24/19 , H01L24/20 , H01L24/96 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16145 , H01L2224/24226 , H01L2224/24246 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/73209 , H01L2224/73267 , H01L2224/97 , H01L2225/06513 , H01L2225/06524 , H01L2225/06586 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01068 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/19043 , H01L2924/00014 , H01L2924/00 , H01L2224/83 , H01L2224/82 , H01L2224/81 , H01L2924/00012
摘要： To pick and place standard first chip size package on a base with a second chip for obtaining an appropriate stacking chip size package than the original chip size package. The package structure has a larger chip size package than the size of the traditional stacking package. Moreover, the terminal pins of the flip chip package may be located on peripheral of LGA package or on array of BGA package.
摘要翻译：在第二个芯片的基座上选择和放置标准的第一个芯片尺寸封装，以获得比原始芯片尺寸封装更适合的堆叠芯片尺寸封装。封装结构具有比传统堆叠封装尺寸更大的芯片尺寸封装。此外，倒装芯片封装的端子引脚可以位于LGA封装的外围或BGA封装的阵列上。

70. 发明申请

US20080085572A1 SEMICONDUCTOR PACKAGING METHOD BY USING LARGE PANEL SIZE 审中-公开
标题翻译：使用大面积尺寸的半导体封装方法
公开(公告)号：US20080085572A1
公开(公告)日：2008-04-10
申请号：US11538896
申请日：2006-10-05
申请人： Wen-Kun Yang , Chih-Wei Lin , Chun-Hui Yu
发明人： Wen-Kun Yang , Chih-Wei Lin , Chun-Hui Yu
IPC分类号： H01L21/60
CPC分类号： H01L21/6835 , H01L21/568 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L2221/68354 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/73267 , H01L2924/01033 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01082 , H01L2924/09701
摘要： The present invention discloses a semiconductor packaging method, comprises steps of back lapping a processed silicon wafer to a desired thickness. Then, the dice are separated from the processed and lapped wafer into a single die. Then, the dice are picked and placed on a tool, an active surface of the dice is attached on the tool. A molding is performed to mold the dice by molding material. The tool is then removed from the dice to form a small unit. The next step is to arrange a plurality of the small units on a carrier in a matrix from. Then, a build-up layer, a re-distribution layer are formed over the dice, followed by forming solder balls on the dice. Finally, the carrier is removed.
摘要翻译：本发明公开了一种半导体封装方法，包括将经处理的硅晶片背面研磨成所需厚度的步骤。然后，将骰子从经处理和研磨的晶片分离成单个模具。然后，骰子被拾取并放置在工具上，骰子的活动表面附着在工具上。进行模制以通过模制材料模制骰子。然后将该工具从骰子中移除以形成小单元。下一步是将多个小单元布置在矩阵中的载体上。然后，在骰子上形成堆积层，再分布层，随后在骰子上形成焊球。最后，载体被移除。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式