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61. 发明授权

US6087262A Method for manufacturing shallow trench isolation structure 有权
标题翻译：浅沟槽隔离结构的制造方法
公开(公告)号：US6087262A
公开(公告)日：2000-07-11
申请号：US189140
申请日：1998-11-09
申请人： Gwo-Shii Yang , Kuo-Tai Huang , Tri-Rung Yew , Water Lur
发明人： Gwo-Shii Yang , Kuo-Tai Huang , Tri-Rung Yew , Water Lur
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/00
CPC分类号： H01L21/31053 , H01L21/76229
摘要： A method for manufacturing shallow trench isolation structure includes the steps of fabricating a self-aligned silicon nitride mask over the trench region so that a kink effect due to the misalignment of mask during a conventional mask-making process can be avoided. Moreover, the silicon nitride mask requires fewer steps and less complicated operations to construct than a conventional reverse tone mask.
摘要翻译：用于制造浅沟槽隔离结构的方法包括以下步骤：在沟槽区域上制造自对准氮化硅掩模，从而可以避免在常规掩模制造工艺期间由于掩模的未对准而产生的扭结效应。此外，与传统的反向色调掩模相比，氮化硅掩模需要更少的步骤和更少的复杂操作来构造。

62. 发明授权

US5976951A Method for preventing oxide recess formation in a shallow trench isolation 失效
标题翻译：在浅沟槽隔离中防止氧化物凹陷形成的方法
公开(公告)号：US5976951A
公开(公告)日：1999-11-02
申请号：US106746
申请日：1998-06-30
申请人： Kuo-Tai Huang , Chih-Hsiang Hsiao , Chao-Yen Chen
发明人： Kuo-Tai Huang , Chih-Hsiang Hsiao , Chao-Yen Chen
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232 , Y10S148/05
摘要： A method for forming an isolating trench in a substrate is disclosed herein. The forgoing method includes the following steps. First, form a first dielectric layer and a second dielectric layer on the substrate subsequently, and then develop a photoresist pattern on the second dielectric layer. Then, etch the substrate, the first dielectric layer and the second dielectric layer to form a trench in the substrate. Next, form a first silicon dioxide layer in the trench followed by removing the photoresist pattern. The next step is to form a third dielectric layer on the second dielectric layer and the first silicon dioxide layer. Subsequently, fill the trench with silicon dioxide to from an oxide trench; then remove the second dielectric layer, a first portion of the third dielectric layer and a portion of the oxide trench with a chemical mechanical polishing (CMP) and a first solution. The third dielectric layer mentioned above includes the first portion of the third dielectric layer and a second portion of the third dielectric layer. Finally, etch the first dielectric layer and the oxide trench to expose the substrate. The second portion of the third dielectric layer is used to prevent an oxide loss in the oxide trench; then the isolating trench being formed thereof.
摘要翻译：本文公开了在衬底中形成隔离沟槽的方法。前述方法包括以下步骤。首先，随后在衬底上形成第一电介质层和第二电介质层，然后在第二电介质层上形成光致抗蚀剂图案。然后，蚀刻衬底，第一介电层和第二介电层，以在衬底中形成沟槽。接下来，在沟槽中形成第一二氧化硅层，然后除去光致抗蚀剂图案。下一步是在第二电介质层和第一二氧化硅层上形成第三电介质层。随后，用二氧化硅填充沟槽至氧化物沟槽; 然后通过化学机械抛光（CMP）和第一溶液去除第二介电层，第三介电层的第一部分和氧化物沟槽的一部分。上述第三电介质层包括第三电介质层的第一部分和第三电介质层的第二部分。最后，蚀刻第一介电层和氧化物沟槽以暴露衬底。第三介质层的第二部分用于防止氧化物沟槽中的氧化物损失; 则形成隔离槽。

63. 发明申请

US20120225529A1 SEALING STRUCTURE FOR HIGH-K METAL GATE AND METHOD OF MAKING 有权
标题翻译：高K金属门的密封结构及其制备方法
公开(公告)号：US20120225529A1
公开(公告)日：2012-09-06
申请号：US13465551
申请日：2012-05-07
申请人： Chieh-Hao Chen , Hao-Ming Lien , Ssu-Yu Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Liang Chen , Chung-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang
发明人： Chieh-Hao Chen , Hao-Ming Lien , Ssu-Yu Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Liang Chen , Chung-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang
IPC分类号： H01L21/336 , H01L21/425
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
摘要翻译：本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域密封层的边缘。

64. 发明授权

US07833853B2 Method of defining gate structure height for semiconductor devices 有权
标题翻译：定义半导体器件栅极结构高度的方法
公开(公告)号：US07833853B2
公开(公告)日：2010-11-16
申请号：US12339483
申请日：2008-12-19
申请人： Ryan Chia-Jen Chen , Yih-Ann Lin , Joseph Lin , Jr Jung Lin , Yu Chao Lin , Chao-Cheng Chen , Kuo-Tai Huang
发明人： Ryan Chia-Jen Chen , Yih-Ann Lin , Joseph Lin , Jr Jung Lin , Yu Chao Lin , Chao-Cheng Chen , Kuo-Tai Huang
IPC分类号： H01L21/28
CPC分类号： H01L29/7848 , H01L21/28079 , H01L21/28088 , H01L21/28123 , H01L29/165 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/6659 , H01L29/66636
摘要： Provided is a method of semiconductor fabrication including process steps allowing for defining and/or modifying a gate structure height during the fabrication process. The gate structure height may be modified (e.g., decreased) at one or more stages during the fabrication by etching a portion of a polysilicon layer included in the gate structure. The method includes forming a coating layer on the substrate and overlying the gate structure. The coating layer is etched back to expose a portion of the gate structure. The gate structure (e.g., polysilicon) is etched back to decrease the height of the gate structure.
摘要翻译：提供了一种半导体制造方法，包括允许在制造过程期间限定和/或修改栅极结构高度的工艺步骤。栅极结构高度可以在制造期间的一个或多个阶段被修改（例如减小），通过蚀刻包括在栅极结构中的多晶硅层的一部分。该方法包括在衬底上形成覆盖层并覆盖栅极结构。将涂层回蚀刻以露出栅极结构的一部分。蚀刻栅极结构（例如，多晶硅）以降低栅极结构的高度。

65. 发明申请

US20060172554A1 METHOD OF FORMING GATE DIELECTRIC LAYER 有权
标题翻译：形成栅介质层的方法
公开(公告)号：US20060172554A1
公开(公告)日：2006-08-03
申请号：US10906008
申请日：2005-01-31
申请人： Yu-Ren Wang , Ying-Wei Yen , Liyuan Cheng , Kuo-Tai Huang
发明人： Yu-Ren Wang , Ying-Wei Yen , Liyuan Cheng , Kuo-Tai Huang
IPC分类号： H01L21/00 , H01L21/31 , H01L21/469
CPC分类号： H01L21/0214 , H01L21/02332 , H01L21/0234 , H01L21/28202 , H01L21/3144 , H01L29/518
摘要： A method for forming a gate dielectric layer is described. A silicon oxide layer is formed on a semiconductor substrate. Then, a first and a second nitrogen doping processes are performed in sequence to the silicon oxide layer using plasma comprising inert gas and gaseous nitrogen to form a gate dielectric layer. The first nitrogen doping process is performed at a lower power, a lower pressure and a higher inert gas to nitrogen gas ratio than those at the second nitrogen doping process. The combination of the deeper nitrogen distribution of the first nitrogen doping process and the shallower nitrogen distribution of the second nitrogen doping process produces a flatter total nitrogen distribution profile so that leakage current from electron tunneling through the gate dielectric layer can be reduced.
摘要翻译：描述了形成栅介质层的方法。在半导体衬底上形成氧化硅层。然后，使用包含惰性气体和气态氮的等离子体，依次对氧化硅层进行第一和第二氮掺杂工艺以形成栅极电介质层。第一氮掺杂过程在低功率，低压和高惰性气体与氮气比之下进行，与第二氮掺杂过程相比。第一氮掺杂过程的较深氮分布和第二氮掺杂过程的较浅氮分布的组合产生更平坦的总氮分布分布，从而可以减少来自电介质穿过栅介质层的漏电流。

66. 发明授权

US06403411B1 Method for manufacturing lower electrode of DRAM capacitor 失效
标题翻译：制造DRAM电容器下电极的方法
公开(公告)号：US06403411B1
公开(公告)日：2002-06-11
申请号：US09208601
申请日：1998-12-08
申请人： Chih-Hsun Chu , Horng-Nan Chern , Kevin Lin , Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
发明人： Chih-Hsun Chu , Horng-Nan Chern , Kevin Lin , Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
IPC分类号： H01L218234
CPC分类号： H01L28/84 , H01L21/76895
摘要： A method for manufacturing the lower electrode of a DRAM capacitor. The method includes depositing polysilicon instead of amorphous silicon to form the lower electrode. Because polysilicon has a higher depositing temperature, it has a higher depositing rate capable of shortening depositing time. After forming the polysilicon lower electrode, the upper portion of the polysilicon layer is transformed into an amorphous layer by bombarding the polysilicon layer with ions to damage its internal structure. Eventually, hemispherical grain silicon is able to grow over the lower electrode, thereby increasing its surface area.
摘要翻译：一种用于制造DRAM电容器的下电极的方法。该方法包括沉积多晶硅而不是非晶硅以形成下电极。由于多晶硅具有较高的沉积温度，因此具有更高的沉积速率，能够缩短沉积时间。在形成多晶硅下电极之后，通过用离子轰击多晶硅层将多晶硅层的上部转变成非晶层，以破坏其内部结构。最终，半球形晶粒硅能够在下电极上生长，从而增加其表面积。

67. 发明授权

US06251783B1 Method of manufacturing shallow trench isolation 失效
标题翻译：制造浅沟槽隔离的方法
公开(公告)号：US06251783B1
公开(公告)日：2001-06-26
申请号：US09189847
申请日：1998-11-12
申请人： Tri-Rung Yew , Kuo-Tai Huang , Gwo-Shii Yang , Water Lur
发明人： Tri-Rung Yew , Kuo-Tai Huang , Gwo-Shii Yang , Water Lur
IPC分类号： H01L21302
CPC分类号： H01L21/31053 , H01L21/76229
摘要： A method of manufacturing shallow trench isolation structures. The method includes the steps of depositing insulating material into the trench of a substrate to form an insulation layer. The substrate has a plurality of active regions, each occupying a different area and having different sizes. In addition, there is a silicon nitride layer on top of each active region. Thereafter, a photoresist layer is then deposited over the insulation layer. Next, a portion of the photoresist layer is etched back to expose a portion of the oxide layer so that the remaining photoresist material forms a cap layer over the recessed area of the insulation layer. Subsequently, using the photoresist cap layer as a mask, the insulation layer is etched to remove a portion of the exposed oxide layer, thereby forming trenches within the oxide layer. After that, the photoresist cap layer is removed. Finally, a chemical-mechanical polishing operation is carried out to polish the insulation layer until the silicon nitride layer is exposed.
摘要翻译：制造浅沟槽隔离结构的方法。该方法包括以下步骤：将绝缘材料沉积到衬底的沟槽中以形成绝缘层。基板具有多个活性区域，每个活性区域占据不同的区域并且具有不同的尺寸。此外，在每个有源区的顶部有一个氮化硅层。此后，然后将光致抗蚀剂层沉积在绝缘层上。接下来，将光致抗蚀剂层的一部分回蚀刻以暴露氧化物层的一部分，使得剩余的光致抗蚀剂材料在绝缘层的凹陷区域上形成覆盖层。随后，使用光致抗蚀剂覆盖层作为掩模，蚀刻绝缘层以去除暴露的氧化物层的一部分，从而在氧化物层内形成沟槽。之后，去除光致抗蚀剂覆盖层。最后，进行化学机械抛光操作以抛光绝缘层，直到暴露氮化硅层。

68. 发明授权

US06251769B1 Method of manufacturing contact pad 失效
标题翻译：制造接触垫的方法
公开(公告)号：US06251769B1
公开(公告)日：2001-06-26
申请号：US09347180
申请日：1999-07-02
申请人： Tri-Rung Yew , Kuo-Tai Huang , Water Lur
发明人： Tri-Rung Yew , Kuo-Tai Huang , Water Lur
IPC分类号： H01L214763
CPC分类号： H01L24/03 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/02639 , H01L21/28525 , H01L21/76814 , H01L21/76879 , H01L21/76895 , H01L21/76897 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01018 , H01L2924/01033 , H01L2924/01082 , H01L2924/14
摘要： A method of manufacturing a contact pad. A substrate having a source/drain region formed therein is provided. A dielectric layer is formed over the substrate. An opening is formed in the dielectric layer and exposes the source/drain region. A selective epitaxial process is performed to form a contact pad in the opening, wherein a top of the contact pad extends onto a surface of the dielectric layer.
摘要翻译：一种制造接触垫的方法。提供其中形成有源极/漏极区的衬底。介电层形成在衬底上。在电介质层中形成开口并使源极/漏极区域露出。执行选择性外延工艺以在开口中形成接触焊盘，其中接触焊盘的顶部延伸到介电层的表面上。

69. 发明授权

US06218238B1 Method of fabricating DRAM capacitor 有权
标题翻译：制造DRAM电容的方法
公开(公告)号：US06218238B1
公开(公告)日：2001-04-17
申请号：US09172458
申请日：1998-10-14
申请人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
发明人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/28568 , H01L21/3211 , H01L27/10852 , H01L28/55
摘要： A method of fabricating a DRAM capacitor uses tungsten nitride in the process of forming a capacitor. The structure of the capacitor is simple and the process is easily executed. Furthermore, the invention provides a method of forming tungsten nitride, comprising a step of implanting nitrogen into a tungsten silicide layer and a step of executing a rapid thermal process under ammonia gas to form a tungsten nitride layer on the surface of the tungsten silicide layer. The method of fabricating a DRAM capacitor comprises forming the tungsten silicide layer after forming a part smaller than a bottom electrode of the capacitor from doped polysilicon and forming tungsten nitride on the surface of the tungsten nitride layer.
摘要翻译：制造DRAM电容器的方法在形成电容器的过程中使用氮化钨。电容器的结构简单，易于执行。此外，本发明提供了一种形成氮化钨的方法，包括将氮气注入到硅化钨层中的步骤以及在氨气下执行快速热处理以在硅化钨层的表面上形成氮化钨层的步骤。制造DRAM电容器的方法包括在从掺杂多晶硅形成小于电容器的底部电极的部分之后形成硅化钨层，并在氮化钨层的表面上形成氮化钨。

70. 发明授权

US6146941A Method for fabricating a capacitor in a semiconductor device 失效
标题翻译：在半导体器件中制造电容器的方法
公开(公告)号：US6146941A
公开(公告)日：2000-11-14
申请号：US128221
申请日：1998-08-03
申请人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
发明人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242 , H01L21/8244 , H01L21/20 , H01L21/44 , H01L21/4763
CPC分类号： H01L27/10852 , H01L28/82
摘要： A fabricating method of a capacitor includes two gates and a commonly used source/drain region formed on a substrate. Then, a process of sell align contact has been applied to make a pitted self align contact window (PSACW) to partly expose the commonly used source/drain region. Then an glue/barrier layer and a lower electrode of the capacitor are formed over the PSACW. Then a dielectric thin film with a material having high dielectric constant is formed over the lower electrode. Then, an upper electrode is formed over the dielectric thin film to complete a capacitor, which has a structure of metal insulator metal with a shape like the PSACW.
摘要翻译：电容器的制造方法包括形成在基板上的两个栅极和常用的源极/漏极区域。然后，已经应用了销售对齐接触的过程，以形成凹陷的自对准接触窗口（PSACW）以部分地暴露常用的源极/漏极区域。然后在PSACW上形成电容器的胶/阻挡层和下电极。然后在下部电极上形成具有高介电常数的材料的电介质薄膜。然后，在电介质薄膜的上方形成上部电极，形成电容器，该电容器具有像PSACW的形状的金属绝缘体金属的结构。

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