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61. 发明授权

US09275950B2 Bead for 2.5D/3D chip packaging application 有权
标题翻译：珠子用于2.5D / 3D芯片封装应用
公开(公告)号：US09275950B2
公开(公告)日：2016-03-01
申请号：US13481974
申请日：2012-05-29
申请人： Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Der-Chyang Yeh , Chuei-Tang Wang
发明人： Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Der-Chyang Yeh , Chuei-Tang Wang
IPC分类号： H01L23/528 , H01L23/552 , H01L23/522
CPC分类号： H01L23/528 , H01L23/5227 , H01L23/552 , H01L2223/6616 , H01L2224/04105 , H01L2224/24137 , H01L2924/14 , H01L2924/15311 , H01L2924/18162
摘要： An integrated circuit package having a multilayer interposer has one or more metal wiring beads provided in the interposer, each of the one or more metal wiring beads has a convoluted wiring pattern that is formed in one of the multiple layers of wiring structures in the interposer, and two terminal end segments connected to the power lines in the integrated circuit package, wherein the one or more metal wiring beads operate as power noise filters.
摘要翻译：具有多层插入器的集成电路封装具有设置在插入件中的一个或多个金属布线珠，所述一个或多个金属布线珠中的每一个具有形成在所述插入件中的所述多层布线结构中的一层中的卷曲布线图案，以及连接到集成电路封装中的电力线的两个终端段，其中所述一个或多个金属布线珠作为功率噪声滤波器起作用。

62. 发明授权

US08810002B2 Vertical metal insulator metal capacitor 有权
标题翻译：垂直金属绝缘子金属电容器
公开(公告)号：US08810002B2
公开(公告)日：2014-08-19
申请号：US12825605
申请日：2010-06-29
申请人： Chewn-Pu Jou , Chen Ho-Hsiang , Fred Kuo , Tse-Hul Lu
发明人： Chewn-Pu Jou , Chen Ho-Hsiang , Fred Kuo , Tse-Hul Lu
IPC分类号： H01L31/119
CPC分类号： H01G4/30 , H01G4/005 , H01G4/306 , H01G13/00 , H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A capacitor includes a first electrode. The first electrode includes a bottom conductive plane and a plurality of first vertical conductive structures. The bottom conductive plane is disposed over a substrate. The capacitor includes a second electrode. The second electrode includes a top conductive plane and a plurality of second vertical conductive structures. The capacitor includes an insulating structure between the first electrode and the second electrode. The first vertical conductive structures and the second vertical conductive structures are interlaced with each other thereby providing higher capacitance density.
摘要翻译：电容器包括第一电极。第一电极包括底部导电平面和多个第一垂直导电结构。底部导电平面设置在衬底上。电容器包括第二电极。第二电极包括顶部导电平面和多个第二垂直导电结构。电容器包括在第一电极和第二电极之间的绝缘结构。第一垂直导电结构和第二垂直导电结构彼此交错，从而提供较高的电容密度。

63. 发明授权

US08665030B2 Voltage-controlled oscillator 有权
标题翻译：压控振荡器
公开(公告)号：US08665030B2
公开(公告)日：2014-03-04
申请号：US13325442
申请日：2011-12-14
申请人： Ying-Ta Lu , Hsien-Yuan Liao , Hsiao-Tsung Yen , Ho-Hsiang Chen , Chewn-Pu Jou
发明人： Ying-Ta Lu , Hsien-Yuan Liao , Hsiao-Tsung Yen , Ho-Hsiang Chen , Chewn-Pu Jou
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1212 , H03B5/124 , H03B5/1852
摘要： A voltage-controlled oscillator circuit includes a first transistor, a second transistor, a first resonator circuit, a second resonator circuit, a first current path and a second current path. A drain of the first transistor is coupled to a gate of the second transistor and to a first end of the first resonator circuit. A source of the first transistor is coupled to the first current path and to a first end of the second resonator circuit. A drain of the second transistor is coupled to a gate of the first transistor and to a second end of the first resonator circuit. A source of the second transistor is coupled to the second current path and a second end of the second resonator circuit.
摘要翻译：压控振荡器电路包括第一晶体管，第二晶体管，第一谐振器电路，第二谐振器电路，第一电流路径和第二电流路径。第一晶体管的漏极耦合到第二晶体管的栅极和第一谐振器电路的第一端。第一晶体管的源极耦合到第一电流路径和第二谐振器电路的第一端。第二晶体管的漏极耦合到第一晶体管的栅极和第一谐振器电路的第二端。第二晶体管的源极耦合到第二电流路径和第二谐振器电路的第二端。

64. 发明申请

US20140029205A1 Band Pass Filter for 2.5D/3D Integrated Circuit Applications 有权
标题翻译： 2.5D / 3D集成电路应用的带通滤波器
公开(公告)号：US20140029205A1
公开(公告)日：2014-01-30
申请号：US13557457
申请日：2012-07-25
申请人： Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Shuo-Mao Chen , Der-Chyang Yeh
发明人： Feng Wei Kuo , Huan-Neng Chen , Chewn-Pu Jou , Shuo-Mao Chen , Der-Chyang Yeh
IPC分类号： H05K7/00 , H01L21/56
CPC分类号： H01L23/3128 , H01L23/642 , H01L23/66 , H01L24/24 , H01L24/82 , H01L25/16 , H01L2223/6627 , H01L2223/6672 , H01L2224/12105 , H01L2224/24195 , H01L2924/181 , H01L2924/19011 , H01L2924/00
摘要： The present disclosure relates to a device and method for a band pass filter with a reduced cost, area penalty, and manufacturing complexity relative to current solutions. An integrated passive device chip comprising a plurality of capacitors embedded in a common molding compound along with a transceiver chip, and arranged within a polymer package. Ultra-thick metallization layers are disposed within the polymer package and configured to couple the integrated passive device chip to the transceiver chip. The ultra-thick metallization layers also form a plurality of transmission lines, wherein the combined integrated passive device chip and transmission lines form a band pass filter with improved frequency response, noise immunity, and cost and area penalty as compared to conventional solutions. The band pass filter may also be coupled to a plurality of solder balls comprising a Flip Chip Ball Grid Array suitable for 2.5D and 3D integrated circuit applications.
摘要翻译：本公开涉及一种带通滤波器的装置和方法，其具有相对于当前解决方案降低的成本，面积损失和制造复杂性。一种集成的无源器件芯片，包括嵌入在共同的模制化合物中的多个电容器以及收发器芯片，并且布置在聚合物封装内。超厚金属化层设置在聚合物封装内并且被配置成将集成的无源器件芯片耦合到收发器芯片。超厚金属化层还形成多条传输线，其中与常规解决方案相比，组合的集成无源器件芯片和传输线形成具有改进的频率响应，抗噪声性以及成本和面积损失的带通滤波器。带通滤波器还可以耦合到多个焊球，其包括适用于2.5D和3D集成电路应用的倒装芯片球栅阵列。

65. 发明授权

US08539388B2 Method and apparatus for low power semiconductor chip layout and low power semiconductor chip 有权
标题翻译：低功耗半导体芯片布局和低功耗半导体芯片的方法和装置
公开(公告)号：US08539388B2
公开(公告)日：2013-09-17
申请号：US12852664
申请日：2010-08-09
申请人： Chewn-Pu Jou , Ming-Tsun Lin , Fu-Lung Hsueh , Shauh-Teh Juang
发明人： Chewn-Pu Jou , Ming-Tsun Lin , Fu-Lung Hsueh , Shauh-Teh Juang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/505 , G06F2217/78
摘要： A layout system is described comprising a layout unit configured to layout cells in a mask design for a semiconductor chip based on library cells for a specified process node; a non-critical path determination unit configured to determine a non-critical path in the semiconductor chip; a cell determination unit configured to determine a group of cells in the mask design that form a part of the non-critical path and determine the corresponding library cell for at least one of the group of cells; a library cell modifying unit configured to modify one or more corresponding library cells to form a corresponding modified library cell; and a cell replacement unit configured to replace a library cell in the group of cells in the mask design that form a part of the non-critical path with the corresponding modified library cell.
摘要翻译：描述布局系统，其包括布局单元，其被配置为基于用于指定处理节点的库单元为半导体芯片的掩模设计布置单元; 非关键路径确定单元，被配置为确定半导体芯片中的非关键路径; 细胞确定单元，被配置为确定所述掩模设计中形成所述非关键路径的一部分的一组细胞，并确定所述细胞组中的至少一个的相应库细胞; 文库细胞修饰单元，被配置为修饰一个或多个相应的文库细胞以形成相应的修饰的文库细胞; 以及细胞置换单元，被配置为用形成所述非关键路径的一部分的掩模设计中的所述细胞组中的库单元替换相应的修改的库单元。

66. 发明申请

US20130147023A1 INTEGRATED CIRCUIT GROUND SHIELDING STRUCTURE 有权
标题翻译：集成电路接地屏蔽结构
公开(公告)号：US20130147023A1
公开(公告)日：2013-06-13
申请号：US13313240
申请日：2011-12-07
申请人： Yu-Ling Lin , Hsiao-Tsung Yen , Ho-Hsiang Chen , Chewn-Pu Jou
发明人： Yu-Ling Lin , Hsiao-Tsung Yen , Ho-Hsiang Chen , Chewn-Pu Jou
IPC分类号： H01L23/552
CPC分类号： H01L23/5227 , H01L23/5225 , H01L23/552 , H01L23/585 , H01L23/645 , H01L25/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides an Integrated Circuit (IC) device. The IC device includes a first die that contains an electronic component. The IC device includes second die that contains a ground shielding structure. The IC device includes a layer disposed between the first die and the second die. The layer couples the first die and the second die together. The present disclosure also involves a microelectronic device. The microelectronic device includes a first die that contains a plurality of first interconnect layers. An inductor coil structure is disposed in a subset of the first interconnect layers. The microelectronic device includes a second die that contains a plurality of second interconnect layers. A patterned ground shielding (PGS) structure is disposed in a subset of the second interconnect layers. The microelectronic device includes an underfill layer disposed between the first and second dies. The underfill layer contains one or more microbumps.
摘要翻译：本公开提供了一种集成电路（IC）装置。 IC器件包括包含电子元件的第一管芯。 IC器件包括包含接地屏蔽结构的第二管芯。 IC器件包括设置在第一管芯和第二管芯之间的层。该层将第一管芯和第二管芯结合在一起。本公开还涉及微电子器件。微电子器件包括包含多个第一互连层的第一管芯。电感线圈结构设置在第一互连层的子集中。微电子器件包括包含多个第二互连层的第二管芯。图案化接地屏蔽（PGS）结构设置在第二互连层的子集中。微电子器件包括设置在第一和第二裸片之间的底部填充层。底层填充层包含一个或多个微胶囊。

67. 发明授权

US08451033B2 Millimeter-wave wideband frequency doubler 有权
标题翻译：毫米波宽带倍频器
公开(公告)号：US08451033B2
公开(公告)日：2013-05-28
申请号：US12967160
申请日：2010-12-14
申请人： Po-Yi Wu , Hsieh-Hung Hsieh , Ho-Hsiang Chen , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
发明人： Po-Yi Wu , Hsieh-Hung Hsieh , Ho-Hsiang Chen , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： H03B19/00
CPC分类号： H03B19/00
摘要： A millimeter-wave wideband frequency doubler stage for use in a distributed frequency doubler includes: a differential input pair of transistors, each transistor having respective gate, drain and source terminals, wherein the source terminals are coupled together to a first power supply node and the drain terminals are coupled together at a first node to a second power supply node; first and second pairs of bandpass gate lines coupled to the gate terminals of the transistors; and a pair of bandpass drain lines coupled to the drain terminals of the transistors.
摘要翻译：用于分布式倍频器的毫米波宽带倍频器级包括：差分输入对晶体管，每个晶体管具有相应的栅极，漏极和源极端子，其中源极端子耦合到第一电源节点，并且漏极端子在第一节点耦合到第二电源节点; 耦合到晶体管的栅极端子的第一和第二对带通栅极线; 以及耦合到晶体管的漏极端子的一对带通漏极线。

68. 发明授权

US08436686B2 Method and apparatus for efficient time slicing 有权
标题翻译：高效时间切片的方法和装置
公开(公告)号：US08436686B2
公开(公告)日：2013-05-07
申请号：US12885974
申请日：2010-09-20
申请人： Feng Wei Kuo , Ying-Ta Lu , Chewn-Pu Jou
发明人： Feng Wei Kuo , Ying-Ta Lu , Chewn-Pu Jou
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03L7/1974 , H03L7/235
摘要： Apparatus for efficient time slicing including a phase lock loop circuit having a voltage controlled oscillator, an auto-frequency calibration circuit coupled with the phase lock loop circuit configured to output a value to select a range of the voltage controlled oscillator, and a burst mode detector connected with the auto-frequency calibration circuit. The burst mode detector having a register adapted to store the output of the auto-frequency calibration circuit.
摘要翻译：一种用于高效时间分片的装置，包括具有压控振荡器的锁相环电路，与锁相环电路耦合的自动频率校准电路，其被配置为输出选择压控振荡器的范围的值，以及突发模式检测器与自动频率校准电路连接。突发模式检测器具有适于存储自动频率校准电路的输出的寄存器。

69. 发明授权

US08295018B2 Transmission-line-based ESD protection 有权
标题翻译：基于传输线路的ESD保护
公开(公告)号：US08295018B2
公开(公告)日：2012-10-23
申请号：US12843082
申请日：2010-07-26
申请人： Hsieh-Hung Hsieh , Po-Yi Wu , Ho-Hsiang Chen , Chewn-Pu Jou , Fu-Lung Hsueh
发明人： Hsieh-Hung Hsieh , Po-Yi Wu , Ho-Hsiang Chen , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： H02H9/00 , H01C7/12 , H02H1/00 , H02H1/04 , H02H3/22 , H02H9/06
CPC分类号： H03F1/52 , H01L27/0288 , H03F3/189 , H03F2200/255 , H03F2200/441 , H03F2200/444
摘要： An ESD protection circuit includes a signal pad, a short circuited shunt stub on-chip with and coupled to the signal pad, an open circuited shunt stub on-chip and coupled to the signal pad.
摘要翻译： ESD保护电路包括信号焊盘，芯片上的短路分流短截线并且耦合到信号焊盘，芯片上的开路分流短截线并耦合到信号焊盘。

70. 发明申请

US20120161285A1 Reducing High-Frequency Signal Loss in Substrates 有权
标题翻译：降低衬底中的高频信号损耗
公开(公告)号：US20120161285A1
公开(公告)日：2012-06-28
申请号：US13412553
申请日：2012-03-05
申请人： Chewn-Pu Jou , Ho-Hsiang Chen
发明人： Chewn-Pu Jou , Ho-Hsiang Chen
IPC分类号： H01L27/06
CPC分类号： H01L23/645 , H01L23/5227 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate of a first conductivity type; and a depletion region in the semiconductor substrate. A deep well region is substantially enclosed by the depletion region, wherein the deep well region is of a second conductivity type opposite the first conductivity type. The depletion region includes a first portion directly over the deep well region and a second portion directly under the deep well region. An integrated circuit device is directly over the depletion region.
摘要翻译：集成电路结构包括第一导电类型的半导体衬底; 和半导体衬底中的耗尽区。深井区域基本上由耗尽区围绕，其中深井区域具有与第一导电类型相反的第二导电类型。耗尽区域包括直接在深井区域上的第一部分和直接位于深井区域下方的第二部分。集成电路器件直接位于耗尽区上方。

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