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61. 发明申请

US20090224405A1 THROUGH VIA PROCESS 有权
标题翻译：通过过程
公开(公告)号：US20090224405A1
公开(公告)日：2009-09-10
申请号：US12044008
申请日：2008-03-07
申请人： Wen-Chih Chiou , Chen-Hua Yu , Weng-Jin Wu , Jung-Chih Hu
发明人： Wen-Chih Chiou , Chen-Hua Yu , Weng-Jin Wu , Jung-Chih Hu
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L23/481 , H01L21/76898 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A through via process is performed on a semiconductor substrate with a contact plug formed in an interlayer dielectric (ILD), and then a via plug is formed in the ILD layer to extend through a portion of the semiconductor substrate, followed forming an interconnection structure electrically connected with the contact plug and the via plug.
摘要翻译：在具有形成在层间电介质（ILD）中的接触插塞的半导体衬底上进行通孔工艺，然后在ILD层中形成通孔以延伸穿过半导体衬底的一部分，然后电连接形成互连结构与接触插头和通孔插头连接。

62. 发明申请

US20090142903A1 CHIP ON WAFER BONDER 有权
标题翻译：芯片在波形焊机上
公开(公告)号：US20090142903A1
公开(公告)日：2009-06-04
申请号：US12054097
申请日：2008-03-24
申请人： Chen-Hua Yu , Jui-Pin Hung , Weng-Jin Wu , Jean Wang , Wen-Chih Chiou
发明人： Chen-Hua Yu , Jui-Pin Hung , Weng-Jin Wu , Jean Wang , Wen-Chih Chiou
IPC分类号： H01L21/30 , B29C65/00
CPC分类号： H01L25/50 , H01L21/67051 , H01L24/28 , H01L24/75 , H01L24/83 , H01L24/94 , H01L2224/8301 , H01L2224/83191 , H01L2224/83192 , H01L2224/8385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01094 , H01L2924/07802 , H01L2924/14 , H01L2924/1461 , H01L2924/15788 , H01L2924/19042 , Y10T156/14 , H01L2924/00
摘要： The present disclosure provides a bonding apparatus. The bonding apparatus includes a cleaning module designed for cleaning chips; and a chip-to-wafer bonding chamber configured to receive the chips from the cleaning module and designed for bonding the chips to a wafer.
摘要翻译：本公开提供了一种接合装置。接合装置包括设计用于清洁芯片的清洁模块; 以及芯片到晶片接合室，其被配置为从所述清洁模块接收所述芯片并被设计用于将所述芯片接合到晶片。

63. 发明授权

US09209157B2 Formation of through via before contact processing 有权
标题翻译：在联系处理之前形成通孔
公开(公告)号：US09209157B2
公开(公告)日：2015-12-08
申请号：US13074883
申请日：2011-03-29
申请人： Wen-Chih Chiou , Chen-Hua Yu , Weng-Jin Wu
发明人： Wen-Chih Chiou , Chen-Hua Yu , Weng-Jin Wu
IPC分类号： H01L21/44 , H01L25/065 , H01L21/768 , H01L23/48 , H01L25/00
CPC分类号： H01L23/481 , H01L21/76898 , H01L25/0657 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06541
摘要： The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads.
摘要翻译：描述了在集成电路（IC）管芯或晶片中形成通孔硅通孔（TSV），其中在接触或金属化处理之前的集成工艺中形成TSV。然后可以在TSV已经就位之后制造触点和接合焊盘，这允许TSV更致密并且允许TSV设计中的更多自由度。通过在TSV和接合焊盘之间提供更密集的连接，单个晶片和管芯可以直接接合在接合焊盘处。因此，导电接合材料通过接合焊盘保持与TSV和其它IC部件的电连接。

64. 发明授权

US08736039B2 Stacked structures and methods of forming stacked structures 有权
标题翻译：堆叠结构和形成堆叠结构的方法
公开(公告)号：US08736039B2
公开(公告)日：2014-05-27
申请号：US11539481
申请日：2006-10-06
申请人： Weng-Jin Wu , Wen-Chih Chiou , Chen-Hua Yu
发明人： Weng-Jin Wu , Wen-Chih Chiou , Chen-Hua Yu
IPC分类号： H01L23/22
CPC分类号： H01L21/78 , H01L23/585 , H01L25/0657 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A stacked structure includes a first die bonded over a second die. The first die has a first die area defined over a first surface. At least one first protective structure is formed over the first surface, around the first die area. At least one side of the first protective structure has at least one first extrusion part extending across a first scribe line around the protective structure. The second die has a second die area defined over a second surface. At least one second protective structure is formed over the second surface, around the second die area. At least one side of the second protective structure has at least one second extrusion part extending across a second scribe line around the protective structure, wherein the first extrusion part is connected with the second extrusion part.
摘要翻译：层叠结构包括在第二管芯上结合的第一管芯。第一管芯具有限定在第一表面上的第一管芯区域。在第一表面，围绕第一模具区域形成至少一个第一保护结构。第一保护结构的至少一侧具有至少一个在保护结构周围延伸穿过第一划线的第一挤压部分。第二模具具有限定在第二表面上的第二模具区域。在第二表面上围绕第二管芯区域形成至少一个第二保护结构。第二保护结构的至少一侧具有至少一个在保护结构周围延伸穿过第二划线的第二挤压部分，其中第一挤压部分与第二挤压部分连接。

65. 发明申请

US20120001337A1 Alignment Mark and Method of Formation 有权
标题翻译：对准标记和形成方法
公开(公告)号：US20120001337A1
公开(公告)日：2012-01-05
申请号：US12827563
申请日：2010-06-30
申请人： Chen-Yu Tsai , Shih-Hui Wang , Chien-Ming Chiu , Chia-Ho Chen , Fang Wen Tsai , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
发明人： Chen-Yu Tsai , Shih-Hui Wang , Chien-Ming Chiu , Chia-Ho Chen , Fang Wen Tsai , Weng-Jin Wu , Jing-Cheng Lin , Wen-Chih Chiou , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号： H01L23/532 , H01L21/71 , H01L23/522
CPC分类号： H01L23/481 , H01L21/30604 , H01L21/6835 , H01L21/76831 , H01L21/76877 , H01L21/76898 , H01L23/544 , H01L2221/68327 , H01L2223/54426 , H01L2224/13
摘要： In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.
摘要翻译：根据实施例，结构包括具有第一区域和第二区域的基板; 穿过基板的第一区域的贯穿基板通孔（TSV）; 在所述衬底的所述第二区域上方的隔离层，所述隔离层具有凹部; 以及在所述隔离层的所述凹部中的导电材料，所述隔离层设置在所述凹部中的所述导电材料和所述基板之间。

66. 发明申请

US20110177655A1 Formation of Through Via before Contact Processing 审中-公开
标题翻译：联络处理前通过形成
公开(公告)号：US20110177655A1
公开(公告)日：2011-07-21
申请号：US13074883
申请日：2011-03-29
申请人： Wen-Chih Chiou , Chen-Hua Yu , Weng-Jin Wu
发明人： Wen-Chih Chiou , Chen-Hua Yu , Weng-Jin Wu
IPC分类号： H01L21/28
CPC分类号： H01L23/481 , H01L21/76898 , H01L25/0657 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06541
摘要： The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads.
摘要翻译：描述了在集成电路（IC）管芯或晶片中形成通孔硅通孔（TSV），其中在接触或金属化处理之前的集成工艺中形成TSV。然后可以在TSV已经就位之后制造触点和接合焊盘，这允许TSV更致密并且允许TSV设计中的更多自由度。通过在TSV和接合焊盘之间提供更密集的连接，单个晶片和管芯可以直接接合在接合焊盘处。因此，导电接合材料通过接合焊盘保持与TSV和其它IC部件的电连接。

67. 发明授权

US07897481B2 High throughput die-to-wafer bonding using pre-alignment 有权
标题翻译：使用预对准的高通量晶片到晶片键合
公开(公告)号：US07897481B2
公开(公告)日：2011-03-01
申请号：US12329304
申请日：2008-12-05
申请人： Wen-Chih Chiou , Weng-Jin Wu , Chen-Hua Yu
发明人： Wen-Chih Chiou , Weng-Jin Wu , Chen-Hua Yu
IPC分类号： H01L21/98
CPC分类号： H01L25/0657 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06541
摘要： A method of forming integrated circuits includes providing a wafer that includes a plurality of dies; aligning a first top die to a first bottom die in the wafer; recording a first destination position of the first top die after the first top die is aligned to the first bottom die; bonding the first top die onto the first bottom die; calculating a second destination position of a second top die using the first destination position; moving the second top die to the second destination position; and bonding the second top die onto a second bottom die without any additional alignment action.
摘要翻译：一种形成集成电路的方法包括提供包括多个管芯的晶片; 将第一顶模与所述晶片中的第一底模对准; 在所述第一顶模与所述第一底模对准之后，记录所述第一顶模的第一目的位置; 将第一顶模连接到第一底模上; 使用所述第一目的地位置计算第二顶模的第二目的位置; 将第二顶部模具移动到第二目的地位置; 以及将所述第二顶模连接到第二底模上而没有任何附加的对准作用。

68. 发明申请

US20100237502A1 Barrier for Through-Silicon Via 有权
标题翻译：通硅硅片的屏障
公开(公告)号：US20100237502A1
公开(公告)日：2010-09-23
申请号：US12631172
申请日：2009-12-04
申请人： Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu
发明人： Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L21/76846 , H01L21/76847 , H01L21/76898 , H01L23/5226 , H01L24/05 , H01L24/06 , H01L2224/0557 , H01L2924/00014 , H01L2924/0002 , H01L2924/01019 , H01L2924/01025 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2224/05552 , H01L2924/00
摘要： A system and a method for protecting through-silicon vias (TSVs) is disclosed. An embodiment comprises forming an opening in a substrate. A liner is formed in the opening and a barrier layer comprising carbon or fluorine is formed along the sidewalls and bottom of the opening. A seed layer is formed over the barrier layer, and the TSV opening is filled with a conductive filler. Another embodiment includes a barrier layer formed using atomic layer deposition.
摘要翻译：公开了一种用于保护硅通孔（TSV）的系统和方法。一个实施例包括在衬底中形成开口。在开口中形成衬垫，并且沿着开口的侧壁和底部形成包含碳或氟的阻挡层。在阻挡层上形成种子层，并且用导电填料填充TSV开口。另一实施例包括使用原子层沉积形成的阻挡层。

69. 发明申请

US20100122456A1 Integrated Alignment and Bonding System 审中-公开
标题翻译：集成对准与接合系统
公开(公告)号：US20100122456A1
公开(公告)日：2010-05-20
申请号：US12272404
申请日：2008-11-17
申请人： Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu
发明人： Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu
IPC分类号： H05K3/30
CPC分类号： H01L24/74 , H01L24/75 , H01L24/80 , H01L24/83 , H01L25/50 , H01L2224/74 , H01L2224/75102 , H01L2224/75251 , H01L2224/75701 , H01L2224/75702 , H01L2224/75705 , H01L2224/75753 , H01L2224/75901 , H01L2224/80055 , H01L2224/80075 , H01L2224/80895 , H01L2224/80896 , H01L2224/83055 , H01L2224/83075 , H01L2224/83801 , H01L2224/94 , H01L2225/06513 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/014 , H01L2924/14 , H01L2924/181 , Y10T29/49124 , Y10T29/4913 , Y10T29/49133 , Y10T29/49135 , H01L2924/00
摘要： A method for bonding includes providing a first die and a second die; scanning at least one of the first die and the second die to determine thickness variations of the at least one of the first die and the second die; placing the second die facing the first die with a first surface of the first die facing a second surface of the second die; aligning the first surface and the second surface parallel to each other using the thickness variations; and bonding the second die onto the first die. The step of aligning the first surface and the second surface includes tilting one of the first die and the second die.
摘要翻译：一种用于接合的方法包括提供第一模具和第二模具; 扫描第一管芯和第二管芯中的至少一个，以确定第一管芯和第二管芯中的至少一个的厚度变化; 将所述第二模具面向所述第一模具，所述第一模具的第一表面面向所述第二模具的第二表面; 使用厚度变化使第一表面和第二表面彼此平行; 以及将所述第二模具接合到所述第一模具上。对准第一表面和第二表面的步骤包括倾斜第一模具和第二模具中的一个。

70. 发明申请

US20090224371A1 Protection for Bonding Pads and Methods of Formation 有权
标题翻译：粘合垫的保护和形成方法
公开(公告)号：US20090224371A1
公开(公告)日：2009-09-10
申请号：US12043023
申请日：2008-03-05
申请人： Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu
发明人： Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu
IPC分类号： H01L23/488 , H01L21/60
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/3171 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/50 , H01L2224/0401 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05684 , H01L2224/06181 , H01L2224/13025 , H01L2224/13099 , H01L2224/13147 , H01L2224/81054 , H01L2224/81203 , H01L2224/81801 , H01L2224/81894 , H01L2224/8192 , H01L2225/06513 , H01L2225/06541 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/10329 , H01L2924/14 , H01L2924/01039 , H01L2924/00
摘要： The formation of bonding pad protective layer over exposed bonding pad materials between stacked integrated circuit (IC) dies or wafers is described in preferred embodiments in which the bonding pad protective layer is formed in the integrated process of forming wafer bonding pads. The bonding pad protective layer prevents the exposed bonding pad materials from oxidation and corrosion in open-air or other harsh environments. By providing a bonding pad protective layer on exposed bonding pad materials, significant product reliability improvement is expected on ICs having a three-dimensional “stacked-die” configuration.
摘要翻译：在堆叠的集成电路（IC）晶片之间的暴露的焊盘材料上的焊盘保护层的形成在其中在形成晶片接合焊盘的集成工艺中形成焊盘保护层的优选实施例中进行了描述。接合焊盘保护层防止暴露的焊盘材料在露天或其他恶劣环境中受到氧化和腐蚀。通过在暴露的焊盘材料上提供焊盘保护层，预期在具有三维“堆叠 - 裸片”结构的IC上可以显着提高产品的可靠性。

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