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61. 发明申请

US20100027329A1 Synchronous Page-Mode Phase-Change Memory with ECC and RAM Cache 失效
标题翻译：具有ECC和RAM缓存的同步页模式相变存储器
公开(公告)号：US20100027329A1
公开(公告)日：2010-02-04
申请号：US12579695
申请日：2009-10-15
申请人： Charles C. Lee , Frank Yu , David Q. Chow
发明人： Charles C. Lee , Frank Yu , David Q. Chow
IPC分类号： G11C11/00 , G11C7/10 , G11C7/00
CPC分类号： G11C8/08 , G11C8/06 , G11C8/12 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2013/0085 , G11C2213/79
摘要： Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks.
摘要翻译：相变存储器（PCM）单元使用高电阻非晶和低电阻晶体状态的合金电阻存储数据。存储单元的设定电流脉冲的时间可以是100 ns，比读取或复位时间长得多。因此，写入时间取决于写入数据并且相对较长。页面模式缓存PCM设备具有高速缓存写入数据的查找表（LUT），该数据稍后被写入PCM存储体阵列。主机数据被锁存到行FIFO中并写入LUT中，从而将写入延迟减少到相对较慢的PCM。主机读取数据可由LUT提供或从PCM存储区中提取。 PCM组和LUT之间的多行页面缓冲区允许使用LUT进行更大的块传输。对LUT中的数据执行纠错码（ECC）检查和生成，将ECC数据写入PCM存储体中隐藏ECC延迟。

62. 发明申请

US20080266991A1 Synchronous Page-Mode Phase-Change Memory with ECC and RAM Cache 失效
标题翻译：具有ECC和RAM缓存的同步页模式相变存储器
公开(公告)号：US20080266991A1
公开(公告)日：2008-10-30
申请号：US11769324
申请日：2007-06-27
申请人： Charles C. Lee , Frank Yu , David Q. Chow
发明人： Charles C. Lee , Frank Yu , David Q. Chow
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1044 , G11C7/1072 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/0085 , G11C2213/79
摘要： Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks.
摘要翻译：相变存储器（PCM）单元使用高电阻非晶和低电阻晶体状态的合金电阻存储数据。存储单元的设定电流脉冲的时间可以是100 ns，比读取或复位时间长得多。因此，写入时间取决于写入数据并且相对较长。页面模式缓存PCM设备具有高速缓存写入数据的查找表（LUT），该数据稍后被写入PCM存储体阵列。主机数据被锁存到行FIFO中并写入LUT中，从而将写入延迟减少到相对较慢的PCM。主机读取数据可由LUT提供或从PCM存储区中提取。 PCM组和LUT之间的多行页面缓冲区允许使用LUT进行更大的块传输。对LUT中的数据执行纠错码（ECC）检查和生成，将ECC数据写入PCM存储体中隐藏ECC延迟。

63. 发明授权

US08200862B2 Low-power USB flash card reader using bulk-pipe streaming with UAS command re-ordering and channel separation 失效
标题翻译：低功耗USB闪存卡阅读器，采用UAS命令重新排序和通道分离的大容量流式传输
公开(公告)号：US08200862B2
公开(公告)日：2012-06-12
申请号：US12887477
申请日：2010-09-21
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F13/12 , G06F13/00 , G06F12/02
CPC分类号： G06F13/28 , G11C13/0004 , G11C16/102 , G11C2216/30 , Y02D10/14
摘要： A flash-card reader improves transmission efficiency by using bulk streaming of multiple pipes. A bulk data-out pipe carries host write data to the card reader and can operate in parallel with a bulk data-in pipe that carries host read data that was read from a flash card attached to the card reader. Status packets do not block data packets since the he status packets are buffered through a separate status pipe, and commands are buffered through a command pipe. Flash data from multiple flash cards are interleaved as separate endpoints that share the bulk data-in pipe. A data in/out streaming state machine controls streaming bulk data through the bulk data-in and data-out pipes, while a status streaming state machine controls streaming status packets through the status pipe. Transaction overhead is reduced using bulk streaming where packets for several commands are combined into the same bulk streams.
摘要翻译：闪存卡读卡器通过使用多个管道的批量流传输来提高传输效率。批量数据输出管道将主机写入数据传送到读卡器，并且可以与承载从附接到读卡器的闪存卡读取的主机读取数据的批量数据输入管并行操作。状态数据包不会阻塞数据包，因为状态数据包通过单独的状态管道进行缓冲，命令通过命令管道缓冲。来自多个闪存卡的闪存数据被交织为共享大容量数据管道的单独端点。数据输入/输出流状态机通过批量数据输入和数据输出管道控制流批量数据，而状态流状态机通过状态管道控制流状态数据包。使用批量流量减少事务开销，其中几个命令的数据包被组合成相同的批量流。

64. 发明申请

US20110213921A1 Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules 有权
标题翻译：命令排队智能存储传输管理器，用于将数据传送到原始NAND闪存模块
公开(公告)号：US20110213921A1
公开(公告)日：2011-09-01
申请号：US13104257
申请日：2011-05-10
申请人： Frank Yu , Charles C. Lee , Abraham C. Ma
发明人： Frank Yu , Charles C. Lee , Abraham C. Ma
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/061 , G06F3/0659 , G06F3/0688 , G06F12/0607 , G06F2212/7208 , G11C13/0004
摘要： A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.
摘要翻译：闪存模块具有通过NVM控制器通过物理块地址（PBA）总线访问的原始NAND闪存芯片。 NVM控制器位于闪存模块或固态硬盘（SSD）的系统板上。 NVM控制器将逻辑块地址（LBA）转换为物理块地址（PBA）。闪存模块的多个通道之间的数据条带化和交织由智能存储事务管理器控制在高电平，而在信道内的进一步的交织和重新映射可由NVM控制器执行。智能存储交换机使用SDRAM缓冲区，在写入闪存之前缓存主机数据。 Q-R指针表存储主机地址的商和余数。剩余部分指向SDRAM中主机数据的位置。命令队列存储主机命令的Q，R。

65. 发明申请

US20100122021A1 USB-Attached-SCSI Flash-Memory System with Additional Command, Status, and Control Pipes to a Smart-Storage Switch 失效
标题翻译： USB附加SCSI闪存系统，带有附加命令，状态和控制管道到智能存储交换机
公开(公告)号：US20100122021A1
公开(公告)日：2010-05-13
申请号：US12651334
申请日：2009-12-31
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F12/00 , G06F12/02 , G06F13/00
CPC分类号： G06F3/0661 , G06F3/0613 , G06F3/0688 , G11C11/5678 , G11C13/0004 , G11C16/102 , G11C2216/30
摘要： An electronic flash-memory card has additional pipes for commands and status messages so that data pipes are not clogged with commands and status messages, allowing for a higher data throughput. The command and status pipes are activated when a UAS/BOT detector detects that a host is using a USB-Attached-SCSI (UAS) mode rather than a Bulk-Only-Transfer (BOT) mode. The host can send additional commands and data without waiting for completion of a prior command when operating in UAS mode but not while operating in BOT mode. A command queue (CQ) in the device re-orders commands for accessing flash memory and merges data in a RAM buffer. Smaller 1 KB USB packets in the data pipes are merged into larger 8 KB payloads in the RAM buffer, allowing for more efficient flash access.
摘要翻译：电子闪存卡具有用于命令和状态消息的附加管道，使得数据管道不被命令和状态消息阻塞，从而允许更高的数据吞吐量。当UAS / BOT检测器检测到主机正在使用USB-Attached-SCSI（UAS）模式而不是Bulk-Only-Transfer（BOT）模式时，命令和状态管道将被激活。主机可以发送附加的命令和数据，而不必在UAS模式下操作时等待先前的命令完成，而不能在BOT模式下运行。设备中的命令队列（CQ）重新命令用于访问闪存的命令，并将数据合并到RAM缓冲区中。数据管道中较小的1 KB USB数据包被合并到RAM缓冲区中的较大的8 KB有效载荷中，从而实现更高效的闪存访问。

66. 发明申请

US20100023682A1 Flash-Memory System with Enhanced Smart-Storage Switch and Packed Meta-Data Cache for Mitigating Write Amplification by Delaying and Merging Writes until a Host Read 有权
标题翻译：具有增强型智能存储交换机和封装元数据缓存的闪存系统，用于通过延迟和合并写入来缓解写入放大，直到主机读取
公开(公告)号：US20100023682A1
公开(公告)日：2010-01-28
申请号：US12576216
申请日：2009-10-08
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/1036 , G06F2212/214 , G06F2212/7203 , G06F2212/7207 , G11C13/0004 , G11C16/102 , G11C19/0808 , G11C2211/5641 , G11C2216/30
摘要： A flash memory solid-state-drive (SSD) has a smart storage switch that reduces write acceleration that occurs when more data is written to flash memory than is received from the host. Page mapping rather than block mapping reduces write acceleration. Host commands are loaded into a Logical-Block-Address (LBA) range FIFO. Entries are sub-divided and portions invalidated when a new command overlaps an older command in the FIFO. Host data is aligned to page boundaries with pre- and post-fetched data filling in to the boundaries. Repeated data patterns are detected and encoded by compressed meta-data codes that are stored in meta-pattern entries in a meta-pattern cache of a meta-pattern flash block. The sector data is not written to flash. The meta-pattern entries are located using a meta-data mapping table. Storing host CRC's for comparison to incoming host data can detect identical data writes that can be skipped, avoiding a write to flash.
摘要翻译：闪存固态驱动器（SSD）具有智能存储交换机，可以减少写入快速写入的速度，而写入速度会比从主机接收到的更多的数据写入闪存。页面映射而不是块映射减少写入加速。主机命令加载到逻辑块地址（LBA）范围FIFO中。当新命令与FIFO中的旧命令重叠时，条目被分割，部分无效。主机数据与页边界对齐，前后获取的数据填充到边界。通过存储在元模式闪存块的元模式高速缓存中的元模式条目中的压缩元数据代码来检测和编码重复的数据模式。扇区数据未写入闪存。使用元数据映射表定位元模式条目。存储主机CRC用于与传入主机数据进行比较可以检测可跳过的相同数据写入，避免写入闪存。

67. 发明申请

US20090193184A1 Hybrid 2-Level Mapping Tables for Hybrid Block- and Page-Mode Flash-Memory System 审中-公开
标题翻译：用于混合块和页模式闪存系统的混合二级映射表
公开(公告)号：US20090193184A1
公开(公告)日：2009-07-30
申请号：US12418550
申请日：2009-04-03
申请人： Frank Yu , Charles C. Lee , Abraham C. Ma , Myeongjin Shin
发明人： Frank Yu , Charles C. Lee , Abraham C. Ma , Myeongjin Shin
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7203 , G06F2212/7208 , G11C11/5628 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C2211/5641
摘要： A hybrid solid-state disk (SSD) has multi-level-cell (MLC) or single-level-cell (SLC) flash memory, or both. SLC flash may be emulated by MLC that uses fewer cell states. A NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Most data is block-mapped and stored in MLC flash, but some critical or high-frequency data is page-mapped to reduce block-relocation copying. A hybrid mapping table has a first-level and a second level. Only the first level is used for block-mapped data, but both levels are used for page-mapped data. The first level contains a block-page bit that indicates if the data is block-mapped or page-mapped. A PBA field in the first-level table maps block-mapped data, while a virtual field points to the second-level table where the PBA and page number is stored for page-mapped data. Page-mapped data is identified by a frequency counter or sector count. SRAM space is reduced.
摘要翻译：混合固态盘（SSD）具有多级单元（MLC）或单级单元（SLC）闪存，或两者兼有。 SLC闪存可能由使用较少单元状态的MLC仿真。 NVM控制器将逻辑块地址（LBA）转换为物理块地址（PBA）。大多数数据被块映射并存储在MLC闪存中，但是一些关键或高频数据被页映射以减少块重定位复制。混合映射表具有第一级和第二级。只有第一级用于块映射数据，但是这两个级别都用于页映射数据。第一级包含一个块页位，指示数据是块映射还是页映射。第一级表中的PBA字段映射块映射数据，而虚拟字段指向存储页面映射数据的PBA和页码的二级表。页面映射数据由频率计数器或扇区计数来标识。 SRAM空间减少。

68. 发明授权

US08452912B2 Flash-memory system with enhanced smart-storage switch and packed meta-data cache for mitigating write amplification by delaying and merging writes until a host read 有权
标题翻译：闪存系统具有增强的智能存储交换机和打包的元数据缓存，用于通过延迟和合并写入来缓解写入，直到主机读取
公开(公告)号：US08452912B2
公开(公告)日：2013-05-28
申请号：US12576216
申请日：2009-10-08
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/1036 , G06F2212/214 , G06F2212/7203 , G06F2212/7207 , G11C13/0004 , G11C16/102 , G11C19/0808 , G11C2211/5641 , G11C2216/30
摘要： A flash memory solid-state-drive (SSD) has a smart storage switch that reduces write acceleration that occurs when more data is written to flash memory than is received from the host. Page mapping rather than block mapping reduces write acceleration. Host commands are loaded into a Logical-Block-Address (LBA) range FIFO. Entries are sub-divided and portions invalidated when a new command overlaps an older command in the FIFO. Host data is aligned to page boundaries with pre- and post-fetched data filling in to the boundaries. Repeated data patterns are detected and encoded by compressed meta-data codes that are stored in meta-pattern entries in a meta-pattern cache of a meta-pattern flash block. The sector data is not written to flash. The meta-pattern entries are located using a meta-data mapping table. Storing host CRC's for comparison to incoming host data can detect identical data writes that can be skipped, avoiding a write to flash.
摘要翻译：闪存固态驱动器（SSD）具有智能存储交换机，可以减少写入快速写入的速度，而写入速度会比从主机接收到的更多的数据写入闪存。页面映射而不是块映射减少写入加速。主机命令加载到逻辑块地址（LBA）范围FIFO中。当新命令与FIFO中的旧命令重叠时，条目被分割，部分无效。主机数据与页边界对齐，前后获取的数据填充到边界。通过存储在元模式闪存块的元模式高速缓存中的元模式条目中的压缩元数据代码来检测和编码重复的数据模式。扇区数据未写入闪存。使用元数据映射表定位元模式条目。存储主机CRC用于与传入主机数据进行比较可以检测可跳过的相同数据写入，避免写入闪存。

69. 发明授权

US08176238B2 Command queuing smart storage transfer manager for striping data to raw-NAND flash modules 有权
标题翻译：命令排队智能存储传输管理器，用于将数据分配到原始NAND闪存模块
公开(公告)号：US08176238B2
公开(公告)日：2012-05-08
申请号：US13104257
申请日：2011-05-10
申请人： Frank Yu , Charles C. Lee , Abraham C. Ma
发明人： Frank Yu , Charles C. Lee , Abraham C. Ma
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0246 , G06F3/061 , G06F3/0659 , G06F3/0688 , G06F12/0607 , G06F2212/7208 , G11C13/0004
摘要： A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.
摘要翻译：闪存模块具有通过NVM控制器通过物理块地址（PBA）总线访问的原始NAND闪存芯片。 NVM控制器位于闪存模块或固态硬盘（SSD）的系统板上。 NVM控制器将逻辑块地址（LBA）转换为物理块地址（PBA）。闪存模块的多个通道之间的数据条带化和交织由智能存储事务管理器控制在高电平，而在信道内的进一步的交织和重新映射可由NVM控制器执行。智能存储交换机使用SDRAM缓冲区，在写入闪存之前缓存主机数据。 Q-R指针表存储主机地址的商和余数。剩余部分指向SDRAM中主机数据的位置。命令队列存储主机命令的Q，R。

70. 发明授权

US08180931B2 USB-attached-SCSI flash-memory system with additional command, status, and control pipes to a smart-storage switch 失效
标题翻译： USB连接的SCSI闪存系统，带有智能存储交换机的附加命令，状态和控制管道
公开(公告)号：US08180931B2
公开(公告)日：2012-05-15
申请号：US12651334
申请日：2009-12-31
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F3/0661 , G06F3/0613 , G06F3/0688 , G11C11/5678 , G11C13/0004 , G11C16/102 , G11C2216/30
摘要： An electronic flash-memory card has additional pipes for commands and status messages so that data pipes are not clogged with commands and status messages, allowing for a higher data throughput. The command and status pipes are activated when a UAS/BOT detector detects that a host is using a USB-Attached-SCSI (UAS) mode rather than a Bulk-Only-Transfer (BOT) mode. The host can send additional commands and data without waiting for completion of a prior command when operating in UAS mode but not while operating in BOT mode. A command queue (CQ) in the device re-orders commands for accessing flash memory and merges data in a RAM buffer. Smaller 1 KB USB packets in the data pipes are merged into larger 8 KB payloads in the RAM buffer, allowing for more efficient flash access.
摘要翻译：电子闪存卡具有用于命令和状态消息的附加管道，使得数据管道不被命令和状态消息阻塞，从而允许更高的数据吞吐量。当UAS / BOT检测器检测到主机正在使用USB-Attached-SCSI（UAS）模式而不是Bulk-Only-Transfer（BOT）模式时，命令和状态管道将被激活。主机可以发送附加的命令和数据，而不必在UAS模式下操作时等待先前的命令完成，而不能在BOT模式下运行。设备中的命令队列（CQ）重新命令用于访问闪存的命令，并将数据合并到RAM缓冲区中。数据管道中较小的1 KB USB数据包被合并到RAM缓冲区中的较大的8 KB有效载荷中，从而实现更高效的闪存访问。

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