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61. 发明申请

US20080251831A1 Semiconductor structure and process for reducing the second bit effect of a memory device 有权
标题翻译：用于降低存储器件的第二位效应的半导体结构和工艺
公开(公告)号：US20080251831A1
公开(公告)日：2008-10-16
申请号：US11786078
申请日：2007-04-10
申请人： Chao-I Wu , Tzu-Hsuan Hsu
发明人： Chao-I Wu , Tzu-Hsuan Hsu
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11568
摘要： A non-volatile memory cell capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in association with at least one electrical dielectric layer, such as an oxide, with a P-type substrate and an N-type channel implanted in the well region of the substrate between two source/drain regions is disclosed. The N-type channel achieves an inversion layer without the application of bias voltage to the gate of the memory cell. A method that implants the N-type channel in the P-type substrate of the cell wherein the N-type channel lowers the un-programmed or programmed voltage threshold of the memory cell to a value lower than would exist without the N-type channel is disclosed. The N-type channel reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened.
摘要翻译：一种非易失性存储单元，其能够存储具有非导电电荷捕获电介质的两比特的信息，例如氮化硅，其与至少一个电介质层（例如氧化物）相关联地与P型衬底相结合，以及公开了在两个源极/漏极区域之间植入衬底的阱区域中的N型沟道。 N型通道实现了反向层，而没有向存储单元的栅极施加偏置电压。一种在单元的P型衬底中嵌入N型沟道的方法，其中N型沟道将存储单元的未编程或编程的电压阈值降低到低于不存在N型沟道的值被披露。 N型通道减小了第二位效应，使得位的编程和非编程电压阈值之间的操作窗口变宽。

62. 发明申请

US20080217679A1 MEMORY UNIT STRUCTURE AND OPERATION METHOD THEREOF 审中-公开
标题翻译：存储单元结构及其操作方法
公开(公告)号：US20080217679A1
公开(公告)日：2008-09-11
申请号：US11683768
申请日：2007-03-08
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： H01L29/792 , G11C11/40
CPC分类号： H01L29/792 , G11C16/0475 , H01L29/513
摘要： A memory unit is proposed. The memory unit includes a Si substrate, a trapping layer formed on the Si substrate, a first and a second doping regions formed in the Si substrate on either side of the trapping layer, a gate formed on the trapping layer, a first oxide layer formed between the gate and the trapping layer, a high-Dit material layer formed between the Si substrate and the trapping layer, and a second oxide layer formed between the high-Dit material layer and the trapping layer, wherein an interface trap density (Dit) between the high-Dit material layer and the Si substrate is in a rang from 1011 cm−2eV−1 to 1013 cm−2eV−1.
摘要翻译：提出了存储单元。存储单元包括Si衬底，形成在Si衬底上的俘获层，形成在捕获层的任一侧上的Si衬底中的第一和第二掺杂区域，形成在俘获层上的栅极，形成的第一氧化物层在栅极和捕获层之间形成在Si衬底和捕获层之间形成的高Dit材料层，以及形成在高Dit材料层和捕获层之间的第二氧化物层，其中界面陷阱密度（Dit）在高Dit材料层和Si衬底之间的距离为10psi -2.2eV至-100nm范围内， 13

63. 发明申请

US20080186779A1 SEMICONDUCTOR DEVICE AND MEMORY AND METHOD OF OPERATING THEREOF 有权
标题翻译：半导体器件和存储器及其操作方法
公开(公告)号：US20080186779A1
公开(公告)日：2008-08-07
申请号：US11670600
申请日：2007-02-02
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C11/34 , H01L27/115
CPC分类号： H01L21/28282 , G11C16/0466 , H01L27/105 , H01L27/11568
摘要： A memory applicable to an embedded memory is provided. The memory includes a substrate, a gate, a charge-trapping gate dielectric layer, a source, and a drain. The gate is disposed above the substrate. The charge-trapping gate dielectric layer is disposed between the gate and the substrate. The source and the drain are disposed in the substrate beside the gate respectively.
摘要翻译：提供了适用于嵌入式存储器的存储器。存储器包括衬底，栅极，电荷俘获栅极电介质层，源极和漏极。栅极设置在衬底上方。电荷捕获栅极电介质层设置在栅极和衬底之间。源极和漏极分别设置在栅极旁边的衬底中。

64. 发明申请

US20080121980A1 Bottom Dielectric Structures and High-K Memory Structures in Memory Devices and Methods for Expanding a Second Bit Operation Window 审中-公开
标题翻译：存储器件中的底部介质结构和高K存储器结构以及用于扩展第二位操作窗口的方法
公开(公告)号：US20080121980A1
公开(公告)日：2008-05-29
申请号：US11425553
申请日：2006-06-21
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0475 , G11C16/14 , H01L29/40117 , H01L29/4234 , H01L29/513 , H01L29/66833
摘要： Methods and structures are described for increasing a memory operation window in a charge trapping memory having a plurality of memory cells in which each memory cell is capable of storing multiple bits per memory cell. In a first aspect of the invention, a first method to increase a memory operation window in a two-bit-per-cell memory is described by applying a positive gate voltage, +Vg, to erase a memory cell to a negative voltage level. Alternatively, a negative gate voltage, −Vg, is applied to the two-bit-per-cell memory for erasing the memory cell to a negative voltage level. A second method to increase a memory operation window is to erase a memory cell to a voltage level that is lower than an initial voltage threshold level. These two erasing methods can be implemented either before a programming step (i.e., a pre-program erase operation) or after a programming step (i.e., a post-program erase operation).
摘要翻译：描述了用于增加具有多个存储器单元的电荷俘获存储器中的存储器操作窗口的方法和结构，其中每个存储器单元能够存储每个存储器单元的多个位。在本发明的第一方面中，通过施加正栅极电压+ Vg来将存储器单元擦除到负电压电平来描述用于增加每位单元2位存储器中的存储器操作窗口的第一种方法。或者，将负栅极电压-Vg施加到每单元存储器2位，以将存储单元擦除为负电压电平。增加存储器操作窗口的第二种方法是将存储器单元擦除到低于初始电压阈值电平的电压电平。这两种擦除方法可以在编程步骤（即，预编程擦除操作）之前或在编程步骤（即，编程后擦除操作）之后实现。

65. 发明申请

US20070297240A1 Methods and Structures for Expanding a Memory Operation Window and Reducing a Second Bit Effect 有权
标题翻译：扩展存储器操作窗口和减少第二位效应的方法和结构
公开(公告)号：US20070297240A1
公开(公告)日：2007-12-27
申请号：US11425482
申请日：2006-06-21
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/0475 , G11C16/14 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/7923
摘要： Methods and structures are described for increasing a memory operation window in a charge trapping memory having a plurality of memory cells in which each memory cell is capable of storing multiple bits per memory cell. In a first aspect of the invention, a first method to increase a memory operation window in a two-bit-per-cell memory is described by applying a positive gate voltage, +Vg, to erase a memory cell to a negative voltage level. Alternatively, a negative gate voltage, −Vg, is applied to the two-bit-per-cell memory for erasing the memory cell to a negative voltage level. A second method to increase a memory operation window is to erase a memory cell to a voltage level that is lower than an initial voltage threshold level. These two erasing methods can be implemented either before a programming step (i.e., a pre-program erase operation) or after a programming step (i.e., a post-program erase operation).
摘要翻译：描述了用于增加具有多个存储器单元的电荷俘获存储器中的存储器操作窗口的方法和结构，其中每个存储器单元能够存储每个存储器单元的多个位。在本发明的第一方面中，通过施加正栅极电压+ Vg来将存储器单元擦除到负电压电平来描述用于增加每位单元2位存储器中的存储器操作窗口的第一种方法。或者，将负栅极电压-Vg施加到每单元存储器2位，以将存储单元擦除为负电压电平。增加存储器操作窗口的第二种方法是将存储器单元擦除到低于初始电压阈值电平的电压电平。这两种擦除方法可以在编程步骤（即，预编程擦除操作）之前或在编程步骤（即，编程后擦除操作）之后实现。

66. 发明申请

US20070291541A1 An Apparatus and Associated Method for Making a Virtual Ground Array Structure that Uses Inversion Bit Lines 有权
标题翻译：用于制造使用反转位线的虚拟地阵列结构的装置和相关方法
公开(公告)号：US20070291541A1
公开(公告)日：2007-12-20
申请号：US11424748
申请日：2006-06-16
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/16 , G11C16/0466 , G11C16/12 , H01L27/0207 , H01L27/115 , H01L27/11568 , Y10S438/954
摘要： A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging.
摘要翻译：虚拟接地阵列结构使用反转位线，以消除对注入位线的需要。结果，可以减小电池尺寸，这可以提供更大的密度和更小的封装。

67. 发明申请

US20070267677A1 SINGLE POLY NON-VOLATILE MEMORY DEVICE WITH INVERSION DIFFUSION REGIONS AND METHODS FOR OPERATING THE SAME 有权
标题翻译：具有反向扩散区域的单个聚合非挥发性存储器件及其操作方法
公开(公告)号：US20070267677A1
公开(公告)日：2007-11-22
申请号：US11383924
申请日：2006-05-17
申请人： Ming-Chang Kuo , Chao-I Wu
发明人： Ming-Chang Kuo , Chao-I Wu
IPC分类号： H01L29/76
CPC分类号： H01L29/7881 , G11C16/0433 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/66825
摘要： A non-volatile memory device comprises a substrate with the dielectric layer formed thereon. A control gate and a floating gate are then formed on top of the dielectric layer. Accordingly, a non-volatile memory device can be constructed using a single poly process that is compatible with conventional CMOS processes. In addition, an assist gate, or assist gates are formed on the dielectric layer next to and between the control gate and floating gate respectively. The assist gates are used to form inversion diffusion regions in the substrate. By using the assist gates to form inversion diffusion regions, the overall size of the device can be reduced, which can improve device density.
摘要翻译：非易失性存储器件包括其上形成有电介质层的衬底。然后在电介质层的顶部形成控制栅极和浮置栅极。因此，可以使用与常规CMOS工艺兼容的单一多工艺来构造非易失性存储器件。此外，辅助栅极或辅助栅极分别形成在控制栅极和浮置栅极之间和之间的电介质层上。辅助栅极用于在衬底中形成反向扩散区域。通过使用辅助栅极形成反向扩散区域，可以减小器件的整体尺寸，这可以提高器件密度。

68. 发明申请

US20070232000A1 FABRICATING METHOD OF A NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的制作方法
公开(公告)号：US20070232000A1
公开(公告)日：2007-10-04
申请号：US11760142
申请日：2007-06-08
申请人： Ming-Chang Kuo , Chao-I Wu
发明人： Ming-Chang Kuo , Chao-I Wu
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L29/42328 , H01L29/42344 , H01L29/7883 , H01L29/7885
摘要： A method of fabricating a non-volatile memory is provided. A stacked structure is formed over a substrate, and the stacked structure has a gate dielectric layer and a floating gate thereon. A first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed over the top and the sidewalls of the stacked structure and the exposed substrate. A charge storage layer covers over the top and sidewalls of the stacked structure. Also, a pair of auxiliary gates is formed over the substrate beside the charge storage layer, and a gap is between the auxiliary gates and the charge storage layer.
摘要翻译：提供了一种制造非易失性存储器的方法。堆叠结构形成在衬底上，堆叠结构在其上具有栅介电层和浮栅。第一电介质层，第二电介质层和第三电介质层分别形成在层叠结构的顶部和侧壁以及暴露的基板上。电荷存储层覆盖层叠结构的顶部和侧壁。此外，在电荷存储层旁边的基板上形成一对辅助栅极，并且在辅助栅极和电荷存储层之间形成间隙。

69. 发明申请

US20070212800A1 Methods for detecting charge effects during semiconductor processing 审中-公开
标题翻译：在半导体加工过程中检测电荷效应的方法
公开(公告)号：US20070212800A1
公开(公告)日：2007-09-13
申请号：US11370362
申请日：2006-03-08
申请人： Chao-I Wu , Ming Lee , Ming-Chang Kuo
发明人： Chao-I Wu , Ming Lee , Ming-Chang Kuo
IPC分类号： H01L21/66
CPC分类号： H01L22/14
摘要： A semiconductor process test structure comprises a gate electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. A charge pump current can be used to detect the charging effect during various processing steps.
摘要翻译：半导体工艺测试结构包括栅电极，电荷捕获层和扩散区。测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。可以使用电荷泵电流来检测各种处理步骤中的充电效果。

70. 发明申请

US20070090448A1 Systems and methods for memory structure comprising embedded flash memory 有权
标题翻译：包括嵌入式闪存的存储器结构的系统和方法
公开(公告)号：US20070090448A1
公开(公告)日：2007-04-26
申请号：US11255483
申请日：2005-10-21
申请人： Chao-I Wu
发明人： Chao-I Wu
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/7923 , H01L21/8221 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578
摘要： A memory structure that combines multiple embedded flash memory. The flash memory can be used, e.g., as air replacement cells or back up memory, or additional memory cells. In one aspect, the flash memory cells are stacked on top of the flash memory cells and the flash memory cells share a gate layer. In another aspect, pairs of stacked flash memory cells are stacked on top of each other with each pair isolated by an isolation oxide. In another aspect, pairs of stacked flash memory cells are stacked on top of each other in an un-isolated configuration.
摘要翻译：一种结合多个嵌入式闪存的存储器结构。闪存可用于例如空气替换单元或备用存储器或附加存储器单元。在一个方面，闪速存储器单元堆叠在闪速存储器单元的顶部上，闪存单元共享一个栅极层。在另一方面，堆叠的闪存单元堆叠在彼此的顶部上，每一对由隔离氧化物隔离。在另一方面，堆叠的闪存单元堆叠在彼此之间的非隔离配置中。

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