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61. 发明申请

US20100091573A1 Nonvolatile Memory And Method With Reduced Program Verify By Ignoring Fastest And/Or Slowest Programming Bits 有权
标题翻译：通过忽略最快和/或最慢的编程位，减少程序验证的非易失性存储器和方法
公开(公告)号：US20100091573A1
公开(公告)日：2010-04-15
申请号：US12249678
申请日：2008-10-10
申请人： Yan Li , Yupin Kawing Fong , Siu Lung Chan
发明人： Yan Li , Yupin Kawing Fong , Siu Lung Chan
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.
摘要翻译：一组非易失性存储器单元通过一系列递增编程脉冲在编程过程中被编程，其中每个脉冲之后是程序验证和可能的编程禁止步骤。在编程过程中，通过延迟启动和过早终止划分多个存储器状态的各种验证电平来提高性能。这相当于跳过组中最快和最慢编程（边缘）单元的验证和禁止步骤。当最快的单元格相对于第一验证电平全部被程序验证时，建立参考脉冲。什么脉冲上的什么验证电平的开始将相对于参考脉冲被延迟。当相对于该给定级别只有预定数量的单元格未被验证时，验证给定验证级别的停止。由边缘单元的过度编程或编程不足引起的任何错误都由纠错码进行校正。

62. 发明申请

US20100017846A1 SERVICE PROCESSING METHOD AND SYSTEM, AND POLICY CONTROL AND CHARGING RULES FUNCTION 有权
标题翻译：服务处理方法与系统，政策控制和收费规则功能
公开(公告)号：US20100017846A1
公开(公告)日：2010-01-21
申请号：US12564558
申请日：2009-09-22
申请人： Shibi Huang , Peng Zhao , Yuxin Mao , Shiyong Tan , Yan Li , Weihua Wei
发明人： Shibi Huang , Peng Zhao , Yuxin Mao , Shiyong Tan , Yan Li , Weihua Wei
IPC分类号： G06F21/24
CPC分类号： H04L47/2433 , H04L12/14 , H04L12/66 , H04L41/0893 , H04L41/0896 , H04L41/5003 , H04M15/66
摘要： A service processing method, a service processing system, and a PCRF entity are disclosed to overcome this defect in the prior art: The prior art is unable to handle services discriminatively according to the policy context information when different services require the same QoS level. The method includes: receiving bearer priority information from a PCRF entity, where the bearer priority information includes: bearer priority information of a service data stream, bearer priority information of an IP-CAN session, and/or bearer priority information of an IP-CAN bearer; and handling services according to the bearer priority information. In the embodiments of the present invention, the policy context information is converted into bearer priority information so that the PCEF handles services according to the bearer priority information. In this way, different services that require the same QoS level are handled discriminatively according to the policy context information.
摘要翻译：公开了一种服务处理方法，服务处理系统和PCRF实体来克服现有技术中的这种缺陷：当不同的服务需要相同的QoS级别时，现有技术不能根据策略上下文信息区别地处理服务。该方法包括：从PCRF实体接收承载优先级信息，其中承载优先级信息包括：业务数据流的承载优先级信息，IP-CAN会话的承载优先级信息和/或IP-CAN承载优先级信息承载人并根据承载优先级信息处理业务。在本发明的实施例中，策略上下文信息被转换为承载优先级信息，使得PCEF根据承载优先级信息来处理业务。以这种方式，根据策略上下文信息来区别地处理需要相同QoS级别的不同服务。

63. 发明授权

US07616499B2 Retention margin program verification 有权
标题翻译：保留保证金计划验证
公开(公告)号：US07616499B2
公开(公告)日：2009-11-10
申请号：US11617541
申请日：2006-12-28
申请人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
发明人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： Data verification in a memory device using a portion of a data retention margin is provided. A bit count is read from the region to determine whether errors will result in the memory. A read in one or more retention margin portions is performed after the normal program verify sequence and if the number of bits in these regions is more than a pre-set the memory will fail verify status. A method of verifying data in a memory device includes the steps of: defining an retention margin between adjacent data thresholds; programming the memory device with data; determining whether bits are present in the data retention margin; and if the number of bits in the retention margin exceeds a threshold, generating an error.
摘要翻译：提供了使用部分数据保留余量的存储器件中的数据验证。从区域读取位计数，以确定错误是否会导致内存。在正常程序验证序列之后执行在一个或多个保留边缘部分中的读取，并且如果这些区域中的位数大于预设，则存储器将失败验证状态。验证存储器件中的数据的方法包括以下步骤：定义相邻数据阈值之间的保留余量; 使用数据对存储设备进行编程; 确定位是否存在于数据保留余量中; 并且如果保留余量中的比特数超过阈值，则产生错误。

64. 发明授权

US07608628B2 Alkylsulphonamide quinolines 有权
标题翻译：烷基磺酰胺喹啉
公开(公告)号：US07608628B2
公开(公告)日：2009-10-27
申请号：US11609166
申请日：2006-12-11
申请人： Thomas R. Simpson , James Kang , Jeffrey S. Albert , Cristobal Alhambra , Gerald M. Koether , James Woods , Yan Li
发明人： Thomas R. Simpson , James Kang , Jeffrey S. Albert , Cristobal Alhambra , Gerald M. Koether , James Woods , Yan Li
IPC分类号： C07D215/38 , A61K31/47 , A61P1/00 , A61P35/00 , A61P37/00 , A61P5/00 , A61P9/00
CPC分类号： C07D215/38 , C07D215/14 , C07D215/52
摘要： Compounds of Formula II wherein R1, A, R2, R3, R4, R5, R8, n, m and q are as described in the specification, pharmaceutically-acceptable salts, methods of making, pharmaceutical compositions containing and methods for using the same.
摘要翻译：式II的化合物，其中R 1，A，R 2，R 3，R 4，R 5，R 8，n，m和q如说明书中所述，药学上可接受的盐，制备方法，药物组合物及其使用方法。

65. 发明申请

US20090237999A1 Different Combinations of Wordline Order and Look-Ahead Read to Improve Non-Volatile Memory Performance 有权
标题翻译：不同组合的字词顺序和前瞻读取，以提高非易失性存储器性能
公开(公告)号：US20090237999A1
公开(公告)日：2009-09-24
申请号：US12051492
申请日：2008-03-19
申请人： Yan Li
发明人： Yan Li
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C2211/5648
摘要： For a non-volatile memory storing three or more bits per cell, pages of data are written in an order where more than one, but less than all of the logical pages that a physical page along a wordline can store are written concurrently. More than one, but less than all of the logical pages that a physical page along a wordline can store are then written concurrently on an adjacent wordline. The process then comes back to the first wordline and writes at least one more logical page. A process is also described where one or more logical pages are written into a physical page along a wordline, after which one or more logical pages are written into a physical page along an adjacent wordline. A read operation is then performed on the first wordline and the resultant read is corrected based on the result of programming the adjacent wordline. This corrected read is then used in writing at least one more logical page in a second programming operation on the first wordline.
摘要翻译：对于每个单元存储三个或更多位的非易失性存储器，以与字线一起的物理页面可以存储的所有逻辑页面多于一个但是小于同时写入的所有逻辑页面的顺序写入数据页。但是，一个字面上可以存储的物理页面上的所有逻辑页面都可以同时写在相邻的字线上。然后，该过程返回到第一个字线，并写入至少一个逻辑页面。还描述了一个过程，其中一个或多个逻辑页面沿着字线被写入物理页面，之后将一个或多个逻辑页面沿着相邻字线写入物理页面。然后对第一字线执行读取操作，并且基于相邻字线的编程结果校正所得到的读取。然后，在第一字线上的第二编程操作中，将该校正后的读取写入至少一个逻辑页面。

66. 发明申请

US20090237998A1 Adaptive Algorithm in Cache Operation with Dynamic Data Latch Requirements 有权
标题翻译：自适应算法在缓存操作中具有动态数据锁存要求
公开(公告)号：US20090237998A1
公开(公告)日：2009-09-24
申请号：US12051462
申请日：2008-03-19
申请人： Yan Li , Anne Pao-Ling Koh
发明人： Yan Li , Anne Pao-Ling Koh
IPC分类号： G11C16/04 , G11C16/06 , G11C7/00
CPC分类号： G11C16/10 , G06F12/0855 , G06F2212/2022 , G11C7/1039 , G11C7/1078 , G11C7/1087 , G11C11/5628 , G11C11/5642 , G11C2207/2245 , G11C2211/5623 , G11C2211/5642 , G11C2211/5643
摘要： A non-volatile memory can perform a first operation (such as a write, for example) on a designated group of one or more addressed pages using a first set of data stored in the corresponding set of data latches and also receive a request for a second operation (such as a read, for example) that also uses some of these corresponding data latches with a second set of data. During the first operation, when at least one latch of each set of the corresponding become available for the second operation, the memory whether there are a sufficient number of the corresponding set of data latches to perform the second operation during the first operation; if not, the second operation is delayed. The memory subsequently can perform the second operation during the first operation when a sufficient number of latches become available; and if, in response to determining whether there are a sufficient number of the corresponding set of data latches to perform the second operation it is determined that there are a sufficient number, performing the second operation during the first operation.
摘要翻译：非易失性存储器可以使用存储在相应的数据锁存器组中的第一组数据来执行一个或多个寻址页面的指定组上的第一操作（例如写入），并且还接收对还使用具有第二组数据的这些相应的数据锁存器中的一些的第二操作（例如读取）。在第一操作期间，当对应的每组的至少一个锁存器变得可用于第二操作时，存储器是否存在足够数量的对应的一组数据锁存器以在第一操作期间执行第二操作; 如果没有，则第二操作被延迟。当足够数量的锁存器变得可用时，存储器随后可以在第一操作期间执行第二操作; 并且如果响应于确定是否存在足够数量的对应的数据锁存器组来执行第二操作，则确定存在足够的数量，在第一操作期间执行第二操作。

67. 发明申请

US20090178028A1 METHOD AND SYSTEM FOR INVOKING JUST-IN-TIME DEBUGGER 有权
标题翻译：用于调用即时调试器的方法和系统
公开(公告)号：US20090178028A1
公开(公告)日：2009-07-09
申请号：US12350820
申请日：2009-01-08
申请人： Steven Francis Best , Yan Li , Yao Qi , Wei Ying Yu , Yong Zheng
发明人： Steven Francis Best , Yan Li , Yao Qi , Wei Ying Yu , Yong Zheng
IPC分类号： G06F11/36
CPC分类号： G06F11/3664 , G06F9/45512 , G06F9/541
摘要： A method and system for invoking Just-In-Time debugger is described, which can provide more efficient JIT debugging for complex code mixed applications. A method for invoking a Just-In-Time (JIT) debugger according to one embodiment includes checking a code type of a code address where a JIT debugging request is triggered from a process of a code-mixed application in response to the JIT debugging request from the process; acquiring corresponding JIT debugging information for different code types of the code-mixed application; and invoking a JIT debugger corresponding to the code type in response to the checked code type of the code address in the process and the acquired corresponding JIT debugging information.
摘要翻译：描述了一种用于调用即时调试器的方法和系统，可以为复杂的代码混合应用程序提供更有效的JIT调试。根据一个实施例的用于调用即时（JIT）调试器的方法包括：响应于JIT调试请求，从代码混合应用程序的过程检查JIT调试请求被触发的代码地址的代码类型从过程中为代码混合应用程序的不同代码类型获取相应的JIT调试信息; 以及响应于所述处理中的代码地址的所检查的代码类型和所获取的相应的JIT调试信息来调用与所述代码类型相对应的JIT调试器。

68. 发明申请

US20090164945A1 INFORMATION PROCESSING DEVICE AND INTEGRATED INFORMATION SYSTEM 审中-公开
标题翻译：信息处理设备和集成信息系统
公开(公告)号：US20090164945A1
公开(公告)日：2009-06-25
申请号：US12337489
申请日：2008-12-17
申请人： Yan Li
发明人： Yan Li
IPC分类号： G06F3/048
CPC分类号： G06F3/04842 , G06F2203/04802
摘要： An information processing device and integrated information system in which many resources are accessible by a simple, clear user interface are provided. The information processing device includes a use interface including displayed faces of a 3D polyhedron icon used to select information to be executed from multiple pieces of information. The multiple pieces of information are allocated to the faces. The 3D polyhedron icon is a parallelepiped for example. By rotating the 3D polyhedron icon horizontally and vertically, a face to be displayed can be switched. The user interface displays an index showing the rotational direction of the 3D polyhedron icon.
摘要翻译：提供了一种信息处理设备和集成信息系统，其中许多资源可通过简单，清晰的用户界面访问。信息处理装置包括使用界面，其包括用于从多条信息中选择要执行的信息的3D多面体图标的显示面。将多条信息分配给面部。 3D多面体图标是例如平行六面体。通过水平和垂直旋转3D多面体图标，可以切换要显示的脸部。用户界面显示显示3D多面体图标旋转方向的索引。

69. 发明申请

US20090136523A1 ANTI-CD26 ANTIBODIES AND METHODS OF USE THEREOF 有权
标题翻译：抗CD26抗体及其使用方法
公开(公告)号：US20090136523A1
公开(公告)日：2009-05-28
申请号：US12263919
申请日：2008-11-03
申请人： Teikichi Aoyagi , Peter Peizhi Luo , Pingyu Zhong , Mark Hsieh , Yan Li , Kevin Caili Wang , Chikao Morimoto
发明人： Teikichi Aoyagi , Peter Peizhi Luo , Pingyu Zhong , Mark Hsieh , Yan Li , Kevin Caili Wang , Chikao Morimoto
IPC分类号： A61K39/395 , C07K16/18 , C12N15/11 , C12N15/00 , C12N5/06
CPC分类号： C07K16/2896 , A61K38/00 , A61K2039/505 , C07K2317/24 , C07K2317/34 , C07K2317/55 , C07K2317/56 , C07K2317/565 , C07K2317/567 , C07K2317/73 , C07K2317/92 , G01N33/574 , G01N2333/70596 , G01N2500/00 , Y02A50/473
摘要： The present invention provides novel anti-CD26 antibodies and other, related polypeptides, as well as novel polynucleotides encoding the antibodies and polypeptides. The invention also provides methods of making the antibodies and polypeptides. Compositions and cells comprising the antibodies or polypeptides are further provided. Methods of using the antibodies and/or polypeptides, such as to inhibit cell proliferation and in the treatment of conditions associated with CD26, are also provided.
摘要翻译：本发明提供新的抗CD26抗体和其它相关多肽，以及编码抗体和多肽的新型多核苷酸。本发明还提供了制备抗体和多肽的方法。进一步提供包含抗体或多肽的组合物和细胞。还提供了使用抗体和/或多肽的方法，例如抑制细胞增殖和治疗与CD26相关的病症。

70. 发明申请

US20090103369A1 Non-Volatile Memory and Method with Shared Processing for an Aggregate of Read/Write Circuits 有权
标题翻译：非易失性存储器和具有共享处理的方法，用于读/写电路的集合
公开(公告)号：US20090103369A1
公开(公告)日：2009-04-23
申请号：US12342679
申请日：2008-12-23
申请人： Raul-Adrian Cernea , Yan Li , Shahzad Khalid , Siu Lung Chan
发明人： Raul-Adrian Cernea , Yan Li , Shahzad Khalid , Siu Lung Chan
IPC分类号： G11C16/06 , G11C11/10
CPC分类号： G11C16/26 , G11C11/5642
摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.
摘要翻译：能够并行地读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。多个读/写电路被组织成一组类似的组件堆叠。考虑冗余电路，例如用于处理每个与多个存储器单元相关联的堆栈之间的数据的处理器。处理器由输入逻辑，锁存器和输出逻辑实现。输入逻辑可以转换从读出放大器或数据锁存器接收到的数据。输出逻辑进一步处理变换的数据以发送到读出放大器或数据锁存器或控制器。这提供了具有最大通用性的基础设施和用于对所感测的数据进行复杂处理和要输入或输出的数据的最少组件。

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