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61. 发明申请

US20070132059A1 Laser fuse with efficient heat dissipation 有权
标题翻译：激光熔丝具有高效散热
公开(公告)号：US20070132059A1
公开(公告)日：2007-06-14
申请号：US11299999
申请日：2005-12-12
申请人： Hao-Yi Tsai , Chao-Hsiang Yang , Shang-Yun Hou , Chia-Lun Tsai , Shin-Puu Jeng
发明人： Hao-Yi Tsai , Chao-Hsiang Yang , Shang-Yun Hou , Chia-Lun Tsai , Shin-Puu Jeng
IPC分类号： H01L29/00
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure having an efficient thermal path and a method for forming the same are provided. The semiconductor structure includes a protection ring over a semiconductor substrate and substantially encloses a laser fuse structure. The laser fuse structure includes a laser fuse and a connection structure connecting the fuse to integrated circuits. The protection ring is thermally coupled to the semiconductor substrate by contacts. The semiconductor structure further includes a metal plate conducting heat generated by a laser beam to the protection ring.
摘要翻译：提供了具有有效的热路径的半导体结构及其形成方法。半导体结构包括半导体衬底上的保护环，并且基本上包围激光熔丝结构。激光熔丝结构包括激光熔丝和将熔丝连接到集成电路的连接结构。保护环通过触点热耦合到半导体衬底。半导体结构还包括将由激光束产生的热量传导到保护环的金属板。

62. 发明授权

US07126225B2 Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling 有权
标题翻译：用于制造具有减少的分层和剥离的半导体晶片的装置和方法
公开(公告)号：US07126225B2
公开(公告)日：2006-10-24
申请号：US10675862
申请日：2003-09-30
申请人： Chao-Yuan Su , Pei-Haw Tsao , Hsin-Hui Lee , Chender Huang , Shang Y. Hou , Shin Puu Jeng , Hao-Yi Tsai , Chenming Hu
发明人： Chao-Yuan Su , Pei-Haw Tsao , Hsin-Hui Lee , Chender Huang , Shang Y. Hou , Shin Puu Jeng , Hao-Yi Tsai , Chenming Hu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area AS is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation AS=S1×S2, where S2 is the width of the second scribe line.
摘要翻译：具有限制测试键放置的自由区域的多层半导体结构。第一和第二划线相交以定义模具的一个角点。第一和第二划痕线是多层结构的一部分，多层结构的至少一层是低k电介质层。自由区域A 1 <1>在第一划线上被定义并且由等式1定义1 D 1 1 ，其中D <1> 是从模具的角点到模具的主要区域的距离，S 1是第一划线的宽度。在第一划线和与模具相邻的第二划线之间的交叉点处限定自由区域A＆S，并且由公式A S S = 其中S 2 <2>是第二划线的宽度。

63. 发明授权

US08125052B2 Seal ring structure with improved cracking protection 有权
标题翻译：密封环结构具有改进的开裂保护
公开(公告)号：US08125052B2
公开(公告)日：2012-02-28
申请号：US11842821
申请日：2007-08-21
申请人： Shin-Puu Jeng , Shih-Hsun Hsu , Shang-Yun Hou , Hao-Yi Tsai , Chen-Hua Yu
发明人： Shin-Puu Jeng , Shih-Hsun Hsu , Shang-Yun Hou , Hao-Yi Tsai , Chen-Hua Yu
IPC分类号： H01L23/00
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor chip comprising a plurality of dielectric layers, wherein the plurality of dielectric layers includes a top dielectric layer; and a first seal ring adjacent edges of the semiconductor chip. The integrated circuit structure further includes a first passivation layer over a top dielectric layer; and a trench extending from a top surface of the first passivation layer into the first passivation layer, wherein the trench substantially forms a ring. Each side of the ring is adjacent to a respective edge of the semiconductor chip. At least one of the plurality of vias has a width greater than about 70 percent of a width of a respective overlying metal line in the plurality of metal lines.
摘要翻译：集成电路结构包括包括多个电介质层的半导体芯片，其中所述多个电介质层包括顶部电介质层; 以及与所述半导体芯片的边缘相邻的第一密封环。集成电路结构还包括在顶部介电层上的第一钝化层; 以及从所述第一钝化层的顶表面延伸到所述第一钝化层中的沟槽，其中所述沟槽基本上形成环。环的每一侧与半导体芯片的相应边缘相邻。所述多个通孔中的至少一个具有大于所述多个金属线中相应的上覆金属线的宽度的约70％的宽度。

64. 发明授权

US08519512B2 Test line placement to improve die sawing quality 有权
公开(公告)号：US08519512B2
公开(公告)日：2013-08-27
申请号：US11525575
申请日：2006-09-22
申请人： Hao-Yi Tsai , Chia-Lun Tsai , Shang-Yun Hou , Shin-Puu Jeng , Shih-Hsun Hsu , Wei-Ti Hsu , Lin-Ko Feng , Chun-Jen Chen
发明人： Hao-Yi Tsai , Chia-Lun Tsai , Shang-Yun Hou , Shin-Puu Jeng , Shih-Hsun Hsu , Wei-Ti Hsu , Lin-Ko Feng , Chun-Jen Chen
IPC分类号： H01L23/544
CPC分类号： H01L21/78 , H01L21/782 , H01L21/784 , H01L21/786 , H01L22/10 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.

65. 发明申请

US20100197114A1 Methods of die sawing 有权
标题翻译：模切方法
公开(公告)号：US20100197114A1
公开(公告)日：2010-08-05
申请号：US12798587
申请日：2010-04-06
申请人： Shin-Puu Jeng , Hao-Yi Tsai
发明人： Shin-Puu Jeng , Hao-Yi Tsai
IPC分类号： H01L21/78
CPC分类号： H01L21/78 , B28D5/022
摘要： A structure includes a substrate having a plurality of scribe line areas surrounding a plurality of die areas. Each of the die areas includes at least one first conductive structure formed over the substrate. Each of the scribe line areas includes at least one active region and at least one non-active region. The active region includes a second conductive structure formed therein. The structure further includes at least one first passivation layer formed over the first conductive structure and second conductive structure, wherein at least a portion of the first passivation layer within the non-active region is removed, whereby die-sawing damage is reduced.
摘要翻译：一种结构包括具有围绕多个管芯区域的多个划线区域的衬底。每个管芯区域包括形成在衬底上的至少一个第一导电结构。每个划线区域包括至少一个有效区域和至少一个非有源区域。有源区包括形成在其中的第二导电结构。该结构还包括形成在第一导电结构和第二导电结构之上的至少一个第一钝化层，其中非活性区域内的第一钝化层的至少一部分被去除，从而降低模切锯损坏。

66. 发明申请

US20090115024A1 Seal ring structure with improved cracking protection and reduced problems 有权
标题翻译：密封环结构具有改进的开裂保护和减少的问题
公开(公告)号：US20090115024A1
公开(公告)日：2009-05-07
申请号：US11933931
申请日：2007-11-01
申请人： Shin-Puu Jeng , Shih-Hsun Hsu , Shang-Yun Hou , Hao-Yi Tsai , Chen-Hua Yu
发明人： Shin-Puu Jeng , Shih-Hsun Hsu , Shang-Yun Hou , Hao-Yi Tsai , Chen-Hua Yu
IPC分类号： H01L23/52
CPC分类号： H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a lower dielectric layer; an upper dielectric layer over the lower dielectric layer; and a seal ring. The seal ring includes an upper metal line in the upper dielectric layer; a continuous via bar underlying and abutting the upper metal line, wherein the continuous via bar has a width greater than about 70 percent of a width of the upper metal line; a lower metal line in the lower dielectric layer; and a via bar underlying and abutting the lower metal line. The via bar has a width substantially less than a half of a width of the lower metal line.
摘要翻译：集成电路结构包括下介电层; 在下介电层上的上电介质层; 和密封环。密封环包括在上介电层中的上金属线; 连续的通孔条，其下面并邻接上部金属线，其中所述连续通孔条具有大于所述上部金属线宽度的约70％的宽度; 下介电层中的下金属线; 以及位于下金属线下方并邻接的通孔条。通孔棒具有基本上小于下金属线宽度的一半的宽度。

67. 发明授权

US08058151B2 Methods of die sawing 有权
标题翻译：模切方法
公开(公告)号：US08058151B2
公开(公告)日：2011-11-15
申请号：US12798587
申请日：2010-04-06
申请人： Shin-Puu Jeng , Hao-Yi Tsai
发明人： Shin-Puu Jeng , Hao-Yi Tsai
IPC分类号： H01L21/46 , H01L21/78 , H01L21/301
CPC分类号： H01L21/78 , B28D5/022
摘要： A structure includes a substrate having a plurality of scribe line areas surrounding a plurality of die areas. Each of the die areas includes at least one first conductive structure formed over the substrate. Each of the scribe line areas includes at least one active region and at least one non-active region. The active region includes a second conductive structure formed therein. The structure further includes at least one first passivation layer formed over the first conductive structure and second conductive structure, wherein at least a portion of the first passivation layer within the non-active region is removed, whereby die-sawing damage is reduced.
摘要翻译：一种结构包括具有围绕多个管芯区域的多个划线区域的衬底。每个管芯区域包括形成在衬底上的至少一个第一导电结构。每个划线区域包括至少一个有源区和至少一个非有源区。有源区包括形成在其中的第二导电结构。该结构还包括形成在第一导电结构和第二导电结构之上的至少一个第一钝化层，其中非活性区域内的第一钝化层的至少一部分被去除，从而降低模切锯损坏。

68. 发明授权

US07776627B2 Flexible structures for interconnect reliability test 有权
标题翻译：用于互连可靠性测试的柔性结构
公开(公告)号：US07776627B2
公开(公告)日：2010-08-17
申请号：US11971072
申请日：2008-01-08
申请人： Shin-Puu Jeng , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N. F. Wu
发明人： Shin-Puu Jeng , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N. F. Wu
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an integrated circuit structure includes forming a test wafer. The step of forming the test wafer includes providing a first semiconductor substrate; and forming a first plurality of unit blocks over the first semiconductor substrate. Each of the first plurality of unit blocks includes a plurality of connection block cells arranged as an array. Each of the connection block cells includes two connection blocks, and a metal line connecting the two connection blocks. The method further includes forming a plurality of unit block boundary lines separating the first plurality of unit blocks from each other; and forming a first plurality of metal lines connecting a portion of the first plurality of unit blocks.
摘要翻译：一种用于形成集成电路结构的方法包括形成测试晶片。形成测试晶片的步骤包括提供第一半导体衬底; 以及在所述第一半导体衬底上形成第一多个单元块。第一多个单元块中的每一个包括被排列成阵列的多个连接块单元。每个连接块单元包括两个连接块和连接两个连接块的金属线。该方法还包括形成将第一多个单元块彼此分离的多个单元块边界线; 以及形成连接所述第一多个单元块的一部分的第一多个金属线。

69. 发明申请

US20070224794A1 Single passivation layer scheme for forming a fuse 有权
标题翻译：用于形成保险丝的单个钝化层方案
公开(公告)号：US20070224794A1
公开(公告)日：2007-09-27
申请号：US11390951
申请日：2006-03-27
申请人： Hao-Yi Tsai , Shang-Yun Hou , Anbiarshy Wu , Chia-Lun Tsai , Shin-Puu Jeng
发明人： Hao-Yi Tsai , Shang-Yun Hou , Anbiarshy Wu , Chia-Lun Tsai , Shin-Puu Jeng
IPC分类号： H01L21/44
CPC分类号： H01L23/5258 , H01L24/11 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/14
摘要： An integrated circuit structure comprising a fuse and a method for forming the same are provided. The integrated circuit structure includes a substrate, an interconnection structure over the substrate, a fuse connected to the interconnection structure, and an anti-reflective coating (ARC) on the fuse. The ARC has an increased thickness and acts as a remaining oxide, and no further remaining passivation layer exists on the ARC.
摘要翻译：提供一种包括熔丝的集成电路结构及其形成方法。集成电路结构包括衬底，衬底上的互连结构，连接到互连结构的熔丝以及熔丝上的抗反射涂层（ARC）。 ARC具有增加的厚度并用作剩余氧化物，并且ARC上不存在进一步的剩余钝化层。

70. 发明授权

US07811866B2 Single passivation layer scheme for forming a fuse 有权
标题翻译：用于形成保险丝的单个钝化层方案
公开(公告)号：US07811866B2
公开(公告)日：2010-10-12
申请号：US11390951
申请日：2006-03-27
申请人： Hao-Yi Tsai , Shang-Yun Hou , Anbiarshy N. F. Wu , Chia-Lun Tsai , Shin-Puu Jeng
发明人： Hao-Yi Tsai , Shang-Yun Hou , Anbiarshy N. F. Wu , Chia-Lun Tsai , Shin-Puu Jeng
IPC分类号： H01L21/82
CPC分类号： H01L23/5258 , H01L24/11 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/14
摘要： An integrated circuit structure comprising a fuse and a method for forming the same are provided. The integrated circuit structure includes a substrate, an interconnection structure over the substrate, a fuse connected to the interconnection structure, and an anti-reflective coating (ARC) on the fuse. The ARC has an increased thickness and acts as a remaining oxide, and no further remaining passivation layer exists on the ARC.
摘要翻译：提供一种包括熔丝的集成电路结构及其形成方法。集成电路结构包括衬底，衬底上的互连结构，连接到互连结构的熔丝以及熔丝上的抗反射涂层（ARC）。 ARC具有增加的厚度并用作剩余氧化物，并且ARC上不存在进一步的剩余钝化层。

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