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61. 发明申请

US20120233366A1 Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System 有权
标题翻译：将非外围组件互连（PCI）资源集成到个人计算机系统中
公开(公告)号：US20120233366A1
公开(公告)日：2012-09-13
申请号：US13477631
申请日：2012-05-22
申请人： Arvind Mandhani , Woojong Han , Ken Shoemaker , Madhu Athreya , Mahesh Wagh , Shreekant S. Thakkar
发明人： Arvind Mandhani , Woojong Han , Ken Shoemaker , Madhu Athreya , Mahesh Wagh , Shreekant S. Thakkar
IPC分类号： G06F13/42
CPC分类号： G06F13/4022 , G06F13/4027 , G06F13/404 , G06F13/4045 , G06F13/42
摘要： In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。第一个接口依次耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将为IP核实现PC协议的头部，以使其能够并入设备中而无需修改。描述和要求保护其他实施例。

62. 发明授权

US08205029B2 Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC) 有权
标题翻译：为芯片上的系统（SoC）提供外设组件互连（PCI）兼容的事务级协议，
公开(公告)号：US08205029B2
公开(公告)日：2012-06-19
申请号：US13230130
申请日：2011-09-12
申请人： Ken Shoemaker , Mahesh Wagh , Woojong Han , Madhu Athreya , Arvind Mandhani , Shreekant S. Thakkar
发明人： Ken Shoemaker , Mahesh Wagh , Woojong Han , Madhu Athreya , Arvind Mandhani , Shreekant S. Thakkar
IPC分类号： G06F13/42 , G06F13/20 , G06F13/36
CPC分类号： G06F13/404 , G06F13/385 , G06F13/4022 , G06F13/4027 , G06F13/4045
摘要： In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。第一接口依次通过一个或多个物理单元耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将实现用于IP核的PC协议的报头以使能无需修改即可并入设备。描述和要求保护其他实施例。

63. 发明申请

US20110271021A1 Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Personal Computer System 有权
标题翻译：将非外围组件互连（PCI）资源集成到个人计算机系统中
公开(公告)号：US20110271021A1
公开(公告)日：2011-11-03
申请号：US13180697
申请日：2011-07-12
申请人： Arvind Mandhani , Woojong Han , Ken Shoemaker , Madhu Athreya , Mahesh Wagh , Shreekant S. Thakkar
发明人： Arvind Mandhani , Woojong Han , Ken Shoemaker , Madhu Athreya , Mahesh Wagh , Shreekant S. Thakkar
IPC分类号： G06F13/42
CPC分类号： G06F13/4022 , G06F13/4027 , G06F13/404 , G06F13/4045 , G06F13/42
摘要： In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。第一个接口依次耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将为IP核实现PC协议的头部，以使其能够并入设备中而无需修改。描述和要求保护其他实施例。

64. 发明授权

US08010731B2 Integrating non-peripheral component interconnect (PCI) resource into a personal computer system 有权
标题翻译：将非外围组件互连（PCI）资源集成到个人计算机系统中
公开(公告)号：US08010731B2
公开(公告)日：2011-08-30
申请号：US12841889
申请日：2010-07-22
申请人： Arvind Mandhani , Woojong Han , Ken Shoemaker , Madhu Athreya , Mahesh Wagh , Shreekant S. Thakkar
发明人： Arvind Mandhani , Woojong Han , Ken Shoemaker , Madhu Athreya , Mahesh Wagh , Shreekant S. Thakkar
IPC分类号： G06F13/42 , G06F13/20 , G06F13/36
CPC分类号： G06F13/4022 , G06F13/4027 , G06F13/404 , G06F13/4045 , G06F13/42
摘要： In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。第一个接口依次耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将为IP核实现PC协议的头部，以使其能够并入设备中而无需修改。描述和要求保护其他实施例。

65. 发明授权

US07594073B2 Method and apparatus for caching memory content on a computing system to facilitate instant-on resuming from a hibernation state 有权
标题翻译：用于在计算系统上缓存存储器内容以便于从休眠状态即时恢复的方法和装置
公开(公告)号：US07594073B2
公开(公告)日：2009-09-22
申请号：US11541113
申请日：2006-09-29
申请人： Ulf R. Hanebutte , Ram Chary , Pradeep Sebastian , Shubha Kumbadakone , Shreekant S. Thakkar
发明人： Ulf R. Hanebutte , Ram Chary , Pradeep Sebastian , Shubha Kumbadakone , Shreekant S. Thakkar
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F1/26 , G06F1/32 , G06G1/00
CPC分类号： G06F12/0866 , Y02D10/13
摘要： The memory content may be cached in the non-volatile cache when a computing system is entering S4 state. The non-volatile cache may be coupled to a bus that connects the disk drive with the disk controller. When resuming from S4 state, the memory content may be read from the non-volatile cache rather than from the slow disk drive, which facilitates instant-on resuming for the system. The caching process may be performed in an OS-transparent manner. During the caching process, data with contiguous addresses may be merged into a block of data. A mapping table may be created and stored in the non-volatile cache which includes multiple entries, each for a block of data. The mapping table facilitates data reading from the non-volatile cache to provide instant-on resuming from S4 state.
摘要翻译：当计算系统进入S4状态时，存储器内容可以被缓存在非易失性高速缓存中。非易失性缓存可以耦合到将盘驱动器与盘控制器连接的总线。当从S4状态恢复时，可以从非易失性高速缓存而不是从慢磁盘驱动器读取存储器内容，这有助于系统的即时恢复。缓存过程可以以OS透明的方式执行。在缓存过程中，具有连续地址的数据可以被合并到一个数据块中。可以创建映射表并将其存储在非易失性高速缓存中，其包括多个条目，每个条目用于数据块。该映射表便于从非易失性高速缓存中进行数据读取，以提供从S4状态的即时恢复。

66. 发明授权

US07467286B2 Executing partial-width packed data instructions 有权
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US07467286B2
公开(公告)日：2008-12-16
申请号：US11126049
申请日：2005-05-09
申请人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： H04Q3/00
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/384 , G06F9/3885
摘要： A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.
摘要翻译：提供了一种用于执行打包数据指令的方法和装置。根据本发明的一个方面，处理器包括寄存器，耦合到寄存器的寄存器重命名单元，耦合到寄存器重命名单元的解码器以及耦合到解码器的部分宽度执行单元。寄存器重命名单元提供架构寄存器文件来存储包括数据元素的打包数据操作数。解码器是对第一和第二组指令进行解码，每组指令在架构寄存器文件中指定一个或多个寄存器。第一组中的每个指令指定要对所有数据元素执行的操作。相比之下，第二组中的每个指令指定仅对数据元素的子集执行的操作。部分宽度执行单元是执行由第一组或第二组指令指定的操作。

67. 发明授权

US06883019B1 Providing information to a communications device 有权
标题翻译：向通信设备提供信息
公开(公告)号：US06883019B1
公开(公告)日：2005-04-19
申请号：US09566620
申请日：2000-05-08
申请人： Uttam K. Sengupta , Shreekant S. Thakkar
发明人： Uttam K. Sengupta , Shreekant S. Thakkar
IPC分类号： G06F13/00 , G06F17/30 , G06Q10/10 , G06F15/16
CPC分类号： G06Q10/109 , G06F17/30867 , G06Q40/04 , Y10S707/99933
摘要： Providing information to a communications device includes determining the relevance of an event to a user based on service choices of the user and, if the event is relevant to the user, determining the relevance of information sources to the event, the information sources including at least data indicating a real-time status of the user, and determining whether to send information about the event to the user based on the information sources.
摘要翻译：向通信设备提供信息包括基于用户的服务选择来确定事件与用户的相关性，并且如果事件与用户相关，确定信息源与事件的相关性，则信息源至少包括指示用户的实时状态的数据，以及基于信息源确定是否向用户发送关于事件的信息。

68. 发明授权

US06289459B1 Processor unique processor number feature with a user controllable disable capability 有权
标题翻译：处理器独特的处理器号码功能，具有用户可控的禁用功能
公开(公告)号：US06289459B1
公开(公告)日：2001-09-11
申请号：US09235054
申请日：1999-01-20
申请人： Stephen A. Fischer , Shreekant S. Thakkar , Robert R. Sullivan , Frederick J. Pollack
发明人： Stephen A. Fischer , Shreekant S. Thakkar , Robert R. Sullivan , Frederick J. Pollack
IPC分类号： G06F1100
CPC分类号： G06F21/73 , G06F11/006 , G06F21/10 , G06F2207/7219 , G06F2221/0744
摘要： A software method of setting a state in a processor regarding whether a processor number encoded in the processor will be available for reading is described. The method comprises prompting the user to enter an indication whether the processor number should be available for reading by a program. Then, setting a state to inhibit the processor number from being read by a program if the indication indicates that the processor number should not be available for reading by the program. For one embodiment, the method further includes testing the indication if a request for the processor number is received, and releasing the processor number if the indication indicates that the processor number is available.
摘要翻译：描述了在处理器中设置处理器中编码的处理器编号是否可用于读取的状态的软件方法。该方法包括提示用户输入处理器号码是否应可供程序读取的指示。然后，如果该指示指示处理器号码不可用于程序读取，则设置状态以阻止处理器号码被程序读取。对于一个实施例，所述方法还包括：如果接收到对所述处理器号码的请求，则测试所述指示，以及如果所述指示指示所述处理器号码可用则释放所述处理器号码。

69. 发明授权

US06275904B1 Cache pollution avoidance instructions 失效
标题翻译：缓存污染回避说明
公开(公告)号：US06275904B1
公开(公告)日：2001-08-14
申请号：US09053385
申请日：1998-03-31
申请人： Srinivas Chennupaty , Shreekant S. Thakkar , Thomas Huff , Vladimir Pentkovski
发明人： Srinivas Chennupaty , Shreekant S. Thakkar , Thomas Huff , Vladimir Pentkovski
IPC分类号： G06F1208
CPC分类号： G06F12/0886 , G06F9/30018 , G06F9/30036 , G06F9/30047 , G06F12/0804 , G06F12/0888
摘要： A computer system and method for providing cache memory management. The computer system comprises a main memory having a plurality of main memory addresses each having a corresponding data entry, and a processor coupled to the main memory. At least one cache memory is coupled to the processor. The at least one cache memory has a cache directory with a plurality of addresses and a cache controller having a plurality of data entries corresponding to the plurality of addresses. The processor receives an instruction having an operand address and determines if the operand address matches one of the plurality of addresses in the cache directory. If so, the processor updates a data entry in the cache controller corresponding to the matched address. Otherwise, a data entry corresponding to the operand address in the main memory is updated.
摘要翻译：一种用于提供高速缓存存储器管理的计算机系统和方法。计算机系统包括具有多个主存储器地址的主存储器，每个主存储器地址都具有对应的数据条目，以及耦合到主存储器的处理器。至少一个高速缓存存储器耦合到处理器。所述至少一个高速缓冲存储器具有具有多个地址的高速缓存目录和具有对应于所述多个地址的多个数据条目的高速缓存控制器。处理器接收具有操作数地址的指令，并确定操作数地址是否匹配高速缓存目录中的多个地址之一。如果是这样，则处理器更新对应于匹配地址的高速缓存控制器中的数据条目。否则，更新与主存储器中的操作数地址相对应的数据条目。

70. 发明授权

US06266769B1 Conversion between packed floating point data and packed 32-bit integer data in different architectural registers 失效
公开(公告)号：US06266769B1
公开(公告)日：2001-07-24
申请号：US09070891
申请日：1998-04-30
申请人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： G06F900
CPC分类号： H03M7/24
摘要： A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the integer format is converted to at least one number in the floating point format. The numbers in the floating point format are placed in a register of a second set of architectural registers in a packed format.

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