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61. 发明授权

US07092236B2 Multilayer chip capacitor 有权
标题翻译：多层片式电容器
公开(公告)号：US07092236B2
公开(公告)日：2006-08-15
申请号：US11068825
申请日：2005-03-02
申请人： Byoung Hwa Lee , Chang Hoon Shim , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Chang Hoon Shim , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/06 , H01G4/005 , H01G4/228
CPC分类号： H01G4/30 , H01G4/232
摘要： A multilayer chip capacitor, which reduces ESL generated due to current flowing through external electrodes and assures an improved mechanical strength. The multilayer chip capacitor includes an upper dummy layer and a lower dummy layer; a plurality of internal electrodes interposed between the upper and lower dummy layers; and external electrodes connected to the internal electrodes, wherein the thickness of the lower dummy layer is smaller than the thickness of the upper dummy layer.
摘要翻译：一种多层片状电容器，其减少由于电流流过外部电极而产生的ESL，并确保改进的机械强度。多层片状电容器包括上虚拟层和下虚拟层; 插入在上下虚拟层之间的多个内部电极; 以及连接到内部电极的外部电极，其中下部虚拟层的厚度小于上部虚拟层的厚度。

62. 发明授权

US09148955B2 Mounting structure of circuit board having multi-layered ceramic capacitor thereon 有权
标题翻译：具有多层陶瓷电容器的电路板的安装结构
公开(公告)号：US09148955B2
公开(公告)日：2015-09-29
申请号：US13481348
申请日：2012-05-25
申请人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
发明人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
IPC分类号： H05K1/18 , H05K1/11 , H05K3/34
CPC分类号： H05K1/111 , H01G4/12 , H01G4/30 , H05K3/3442 , H05K2201/10015 , H05K2201/2045 , Y02P70/611 , Y02P70/613
摘要： Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon. The mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, in which a dielectric layer on which inner electrodes are disposed is stacked and external electrode terminals connecting the inner electrodes in parallel are disposed on both ends thereof, wherein the inner electrodes of the multi-layered ceramic capacitor and the circuit board are disposed so as to be a horizontal direction to connect the external electrode terminals with a land on the circuit board by a conductive material and a ratio of a bonding area ASOLEDER of the conductive material to the area AMLCC of the external electrode terminals AMLCC is set to be less than 1.4, thereby remarkably reducing the vibration noise.
摘要翻译：这里公开了一种其上具有多层陶瓷电容器的电路板的安装结构。其上设置有多层陶瓷电容器的电路板的安装结构，其中布置有内部电极的电介质层，并且将其内部电极并联连接的外部电极端子设置在其两端，其中内部电极将多层陶瓷电容器和电路板设置成水平方向，以通过导电材料将导电材料的外部电极端子与电路板上的焊盘接合，并且将导电材料的接合面积ASOLEDER与外部电极端子AMLCC的面积AMLCC被设定为小于1.4，从而显着地降低了振动噪声。

63. 发明授权

US08630083B2 Multi-layered capacitor and manufacturing method thereof 有权
标题翻译：多层电容器及其制造方法
公开(公告)号：US08630083B2
公开(公告)日：2014-01-14
申请号：US13447692
申请日：2012-04-16
申请人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
发明人： Young Ghyu Ahn , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
IPC分类号： H01G4/228 , H01G4/06
CPC分类号： H01G4/232 , H01G4/12 , H01G4/30 , H01G4/35
摘要： A multi-layered capacitor includes a capacitor element in which a plurality of dielectric layers are multi-layered, and which comprises a first inner electrode and a second inner electrode that are alternately formed on neighboring dielectric layers of the plurality of dielectric layers, a first external electrode and a second external electrode which are formed on an outside surface of the capacitor element to be electrically connected to the first inner electrode and the second inner electrode, respectively, and a deformation suppressing electrode which is formed on the outside surface of the capacitor element and separated from the first external electrode and the second external electrode to be electrically isolated from the first inner electrode and the second inner electrode.
摘要翻译：多层电容器包括电容器元件，其中多个电介质层是多层的，并且包括交替地形成在多个电介质层的相邻电介质层上的第一内电极和第二内电极，第一外部电极和第二外部电极，分别形成在电容器元件的外表面上以与第一内部电极和第二内部电极电连接;变形抑制电极，形成在电容器的外表面上并且与第一外部电极和第二外部电极分离以与第一内部电极和第二内部电极电隔离。

64. 发明申请

US20130319741A1 LAMINATED CHIP ELECTRONIC COMPONENT, BOARD FOR MOUNTING THE SAME, AND PACKING UNIT THEREOF 有权
标题翻译：层压电子元件，用于安装的组件及其包装单元
公开(公告)号：US20130319741A1
公开(公告)日：2013-12-05
申请号：US13588696
申请日：2012-08-17
申请人： Young Ghyu AHN , Sang Soo Park , Min Cheol Park , Se Hwa Jeong
发明人： Young Ghyu AHN , Sang Soo Park , Min Cheol Park , Se Hwa Jeong
IPC分类号： H01G4/12 , H05K7/00 , H05K1/18
CPC分类号： H01G4/005 , H01G4/30 , H05K1/0271 , H05K1/111 , H05K3/3442 , H05K2201/09427 , H05K2201/10015 , H05K2201/10636 , H05K2201/2045 , Y02P70/611
摘要： A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer.
摘要翻译：层叠芯片电子部件包括：陶瓷体，其包括内部电极和电介质层; 形成为在长度方向上覆盖陶瓷体的两端部的外部电极; 其中内部电极以相对的方式设置在其间插入电介质层的有源层以形成电容; 以及在有源层的厚度方向的上部和下部形成的上部和下部覆盖层，所述下部覆盖层的厚度大于上部覆盖层的厚度。

65. 发明授权

US08456797B1 Laminated chip electronic component, board for mounting the same, and packing unit thereof 有权
公开(公告)号：US08456797B1
公开(公告)日：2013-06-04
申请号：US13588876
申请日：2012-08-17
申请人： Young Ghyu Ahn , Min Cheol Park , Doo Young Kim , Sang Soo Park
发明人： Young Ghyu Ahn , Min Cheol Park , Doo Young Kim , Sang Soo Park
IPC分类号： H01G4/06 , H01G4/005
摘要： A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; first and second external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer; and additional electrode layers disposed irrespective of a formation of capacitance within the lower cover layer.

66. 发明申请

US20120327557A1 CHIP TYPE LAMINATED CAPACITOR 有权
标题翻译：芯片型层压电容器
公开(公告)号：US20120327557A1
公开(公告)日：2012-12-27
申请号：US13531242
申请日：2012-06-22
申请人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Young Hoon Song , Mi Hee Lee
发明人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Young Hoon Song , Mi Hee Lee
IPC分类号： H01G4/12
CPC分类号： H01G4/1272 , H01G2/065 , H01G4/005 , H01G4/12 , H01G4/228 , H01G4/232 , H01G4/30
摘要： There is provided a chip type laminated capacitor including: a ceramic body formed by laminating a dielectric layer having a thickness equal to 10 or more times an average particle diameter of a grain included therein and being 3 μm or less; first and second outer electrodes; a first inner electrode having one end forming a first margin together with one end surface of the ceramic body at which the second outer electrode is formed and the other end leading to the first outer electrode; and a second inner electrode having one end forming a second margin together with the other end surface of the ceramic body at which the first outer electrode is formed and the other end leading to the second outer electrode, wherein the first and second margins have different widths under a condition that they are 200 μm or less.
摘要翻译：提供一种芯片型层叠电容器，其包括：陶瓷体，其通过层叠厚度等于其中包含的晶粒的平均粒径的10倍以上且为3μm以下的电介质层而形成; 第一和第二外部电极; 第一内部电极，其一端与形成有第二外部电极的陶瓷体的一个端面一起形成第一边缘，而另一端通向第一外部电极; 以及第二内部电极，其一端与形成有第一外部电极的陶瓷体的另一个端面一起形成第二边缘，另一端通向第二外部电极，其中第一和第二边缘具有不同的宽度在200μm以下的条件下。

67. 发明申请

US20120275081A1 MULTI-LAYERED CAPACITOR AND MANUFACTURING METHOD THEREOF 有权
标题翻译：多层电容器及其制造方法
公开(公告)号：US20120275081A1
公开(公告)日：2012-11-01
申请号：US13447692
申请日：2012-04-16
申请人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
发明人： Young Ghyu AHN , Byoung Hwa Lee , Min Cheol Park , Sang Soo Park , Dong Seok Park
IPC分类号： H01G4/30
CPC分类号： H01G4/232 , H01G4/12 , H01G4/30 , H01G4/35
摘要： A multi-layered capacitor includes a capacitor element in which a plurality of dielectric layers are multi-layered, and which comprises a first inner electrode and a second inner electrode that are alternately formed on neighboring dielectric layers of the plurality of dielectric layers, a first external electrode and a second external electrode which are formed on an outside surface of the capacitor element to be electrically connected to the first inner electrode and the second inner electrode, respectively, and a deformation suppressing electrode which is formed on the outside surface of the capacitor element and separated from the first external electrode and the second external electrode to be electrically isolated from the first inner electrode and the second inner electrode.
摘要翻译：多层电容器包括电容器元件，其中多个电介质层是多层的，并且包括交替地形成在多个电介质层的相邻电介质层上的第一内电极和第二内电极，第一外部电极和第二外部电极，分别形成在电容器元件的外表面上以与第一内部电极和第二内部电极电连接;变形抑制电极，形成在电容器的外表面上并且与第一外部电极和第二外部电极分离以与第一内部电极和第二内部电极电隔离。

68. 发明授权

US08233263B2 Multilayer chip capacitor for improving ESR and ESL 有权
标题翻译：用于改善ESR和ESL的多层片式电容器
公开(公告)号：US08233263B2
公开(公告)日：2012-07-31
申请号：US12248476
申请日：2008-10-09
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/005 , H01G4/06 , H01G4/228
CPC分类号： H01G4/012 , H01G4/232 , H01G4/30
摘要： A multilayer chip capacitor includes a capacitor body including a stack of a plurality of dielectric layers and having first and second side faces and first and second end faces, a plurality of external electrodes of opposite polarity alternated on each of the first and second side faces, and a plurality of internal electrodes each including one or two leads extending to an outer face of the capacitor body and respectively connected to the external electrodes. A horizontal distance between leads of the internal electrodes of opposite polarity adjacent to each other in a stack direction is longer than a pitch between the external electrodes of opposite polarity adjacent to each other on the same side face of the capacitor body.
摘要翻译：多层片状电容器包括电容器主体，其包括多个电介质层的叠层，并且具有第一和第二侧面以及第一和第二端面，多个相反极性的外部电极在第一和第二侧面中的每一个上交替，以及多个内部电极，每个内部电极包括延伸到电容器主体的外表面并分别连接到外部电极的一个或两个引线。在堆叠方向上彼此相邻的内部电极的引线之间的水平距离比在电容器主体的同一侧面上彼此相邻的外部电极之间的间距长。

69. 发明授权

US08149565B2 Circuit board device and integrated circuit device 有权
标题翻译：电路板装置和集成电路装置
公开(公告)号：US08149565B2
公开(公告)日：2012-04-03
申请号：US12421953
申请日：2009-04-10
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hong Yeon Cho , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hong Yeon Cho , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G15/00
CPC分类号： H05K1/0231 , H01G2/065 , H01G4/35 , H05K2201/09318 , H05K2201/09481 , H05K2201/10636 , H05K2201/10969 , Y02P70/611
摘要： A circuit board device includes a circuit board comprising a mounting area, and first and second power lines and a ground pad formed on the mounting area, and a vertical multilayer chip capacitor (MLCC) comprising a capacitor body, a plurality of first and second polarity inner electrodes, first and second outer electrodes, and a third outer electrode, wherein the first and second power lines are separately disposed on the mounting area, connected to the first and second outer electrodes, and electrically connected to each other only by the vertical MLCC, and the ground pad is disposed between the first and second power lines and connected to the third outer electrode.
摘要翻译：一种电路板装置，包括：电路板，包括安装区域;以及第一和第二电力线以及形成在所述安装区域上的接地焊盘;以及垂直多层片状电容器（MLCC），其包括电容器本体，多个第一和第二极性内部电极，第一外部电极和第二外部电极以及第三外部电极，其中第一和第二电力线分别设置在安装区域上，连接到第一和第二外部电极，并且仅通过垂直MLCC 并且接地焊盘设置在第一和第二电源线之间并且连接到第三外部电极。

70. 发明授权

US08081416B2 Multilayer chip capacitor 有权
标题翻译：多层片式电容器
公开(公告)号：US08081416B2
公开(公告)日：2011-12-20
申请号：US12267112
申请日：2008-11-07
申请人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Sung Kwon Wi , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/005 , H01G4/228
CPC分类号： H01G4/30 , H01G4/012 , H01G4/232
摘要： A multilayer chip capacitor includes a capacitor body provided by a stack of a plurality of dielectric layers, a plurality of internal electrodes disposed in the capacitor body such that the internal electrodes of opposite polarities are alternately disposed to face each other with the dielectric layer interposed between each facing set of the internal electrodes, and a plurality of external electrodes disposed on an outer face of the capacitor body and electrically connected with the internal electrode. Each of the plurality of internal electrodes includes a main electrode part, and at least one lead extending from the main electrode part to a side face of the capacitor body and connected to a corresponding one of the external electrodes. The lead extends to the corresponding external electrode to be inclined with respect to the main electrode part thereof.
摘要翻译：多层片状电容器包括：由多个电介质层的堆叠体构成的电容器主体，设置在电容器主体中的多个内部电极，使得相互极性的内部电极交替地配置成彼此面对，其中介电层介于每个面对的内部电极组，以及多个外部电极，设置在电容器主体的外表面上并与内部电极电连接。多个内部电极中的每一个包括主电极部分和从电极主体的主电极部分延伸到侧面的至少一个引线，并连接到对应的一个外部电极。引线延伸到对应的外部电极，以相对于其主电极部分倾斜。

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