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61. 发明授权

US07383367B2 Progressive extended compression mask for dynamic trace 有权
标题翻译：逐行扩展压缩掩码，用于动态跟踪
公开(公告)号：US07383367B2
公开(公告)日：2008-06-03
申请号：US11566757
申请日：2006-12-05
申请人： Lewis Nardini , Manisha Agarwala , John M. Johnsen
发明人： Lewis Nardini , Manisha Agarwala , John M. Johnsen
IPC分类号： G06F3/00 , G06F13/12 , G06F9/455 , G06R31/28
CPC分类号： G06F11/3636 , G06F11/3476
摘要： This invention provides trace address compression by comparing respective bytes of a current trace address with a stored prior trace address. Only the least significant bytes of the current trace address that do not match the stored prior trace address or are less significant than any section of the current trace address that does not match the stored prior trace address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The prior trace address may be updated with the current trace address if there is a complete mismatch.
摘要翻译：本发明通过将当前跟踪地址的各个字节与存储的先前跟踪地址进行比较来提供跟踪地址压缩。只有当前跟踪地址中与存储的先前跟踪地址不匹配或者比当前跟踪地址中与存储的先前跟踪地址不匹配的任何部分不太重要的最低有效字节被传送。这有时会减少需要传输的数据量。如果存在完全不匹配，则可以使用当前跟踪地址更新先前的跟踪地址。

62. 发明申请

US20070294590A1 COMPRESSION SCHEME TO REDUCE THE BANDWIDTH REQUIREMENTS FOR CONTINUOUS TRACE STREAM ENCODING OF SYSTEM PERFORMANCE 审中-公开
标题翻译：压缩方案，以减少系统性能连续跟踪编码的带宽要求
公开(公告)号：US20070294590A1
公开(公告)日：2007-12-20
申请号：US11383697
申请日：2006-05-16
申请人： Manisha Agarwala , John M. Johnsen , Lewis Nardini
发明人： Manisha Agarwala , John M. Johnsen , Lewis Nardini
IPC分类号： G06F11/00
CPC分类号： G06F11/26
摘要： A system and method of counting event patterns in order to reduce the bandwidth of event data sent to a monitoring computer. The event patterns are output as one or more data packets indicating the event pattern and a number of occurrences of the pattern.
摘要翻译：计数事件模式的系统和方法，以减少发送到监控计算机的事件数据的带宽。事件模式作为一个或多个数据分组输出，指示事件模式和模式的出现次数。

63. 发明授权

US07219333B2 Maintaining coherent synchronization between data streams on detection of overflow 有权
标题翻译：在检测到溢出时保持数据流之间的一致同步
公开(公告)号：US07219333B2
公开(公告)日：2007-05-15
申请号：US10301893
申请日：2002-11-22
申请人： Manisha Agarwala , John M. Johnsen
发明人： Manisha Agarwala , John M. Johnsen
IPC分类号： G06F9/44 , G06F11/00
CPC分类号： G06F11/3466 , G06F11/301 , G06F11/3632 , G06F11/3636 , G06F11/3656
摘要： Trace data streams are generated for tracing target processor activity. Various trace data streams are synchronized using markers called sync points. The sync points provide a unique identifier field and a context to the data that will follow it. All trace data streams may generate a sync point with this unique identifier. These unique identifiers allow synchronization between multiple trace data streams. When multiple trace data streams are on, it is possible that the data input rate may be higher than the data output rate. If synchronization is lost in such a case, there must be a scheme to resynchronize the streams. This invention is a technique for this needed resynchronization.
摘要翻译：生成跟踪数据流以跟踪目标处理器活动。使用称为同步点的标记来同步各种跟踪数据流。同步点提供唯一的标识符字段和跟随它的数据的上下文。所有跟踪数据流可以产生具有该唯一标识符的同步点。这些唯一标识符允许在多个跟踪数据流之间进行同步。当多个跟踪数据流打开时，数据输入速率可能高于数据输出速率。如果在这种情况下同步丢失，则必须有一个方案来重新同步流。本发明是用于该需要的再同步的技术。

64. 发明申请

US20060279443A1 Trading Off Visibility for Volume of Data When Profiling Memory Events 有权
标题翻译：对内存事件进行分析时交易数据量的可见性
公开(公告)号：US20060279443A1
公开(公告)日：2006-12-14
申请号：US11383545
申请日：2006-05-16
申请人： Manisha Agarwala , Oliver Sohm
发明人： Manisha Agarwala , Oliver Sohm
IPC分类号： H03M1/00
CPC分类号： G06F11/3636
摘要： When tracing memory events the required bandwidth may be reduced by forming a logical OR of several memory event signals to determine the location of memory events. A second trace run may be made after this, tracing only the limited portions of the application where the first run indicated possible problems.
摘要翻译：当跟踪存储器事件时，可以通过形成几个存储器事件信号的逻辑或来确定存储器事件的位置来减少所需的带宽。可以在此之后进行第二次跟踪运行，仅跟踪应用程序的有限部分，其中第一次运行指示可能的问题。

65. 发明申请

US20060265577A1 REAL-TIME MONITORING, ALIGNMENT, AND TRANSLATION OF CPU STALLS OR EVENTS 有权
标题翻译： CPU STALLS或事件的实时监控，对准和翻译
公开(公告)号：US20060265577A1
公开(公告)日：2006-11-23
申请号：US11383361
申请日：2006-05-15
申请人： Oliver Sohm , Gary Swoboda , Manisha Agarwala
发明人： Oliver Sohm , Gary Swoboda , Manisha Agarwala
IPC分类号： G06F9/44
CPC分类号： G01R31/31705 , G06F11/3636
摘要： A system and method of tracing a group of processor events in real-time in order to enable a programmer to debug and profile the operation and execution of code on the processor. This may be accomplished by running one or more traces on the same or different groups of processor events in order to gain a full understanding of how code is being executed by the processor.
摘要翻译：实时跟踪一组处理器事件的系统和方法，以使程序员能够对处理器上的代码的操作和执行进行调试和配置。这可以通过在相同或不同的处理器事件组上运行一个或多个迹线来完成，以便充分了解处理器如何执行代码。

66. 发明授权

US07100151B2 Recovery from corruption using event offset format in data trace 有权
公开(公告)号：US07100151B2
公开(公告)日：2006-08-29
申请号：US10302024
申请日：2002-11-22
申请人： John M. Johnsen , Manisha Agarwala , Maria B. H. Gill
发明人： John M. Johnsen , Manisha Agarwala , Maria B. H. Gill
IPC分类号： G06F9/44
CPC分类号： G06F11/3636 , G06F11/3652
摘要： A method of tracing data processor activity with recover from detection of trace stream corruption. If the first trace data following detection of corruption is not a program counter sync point, then the trace transmits an indication of the current program counter address in an offset format from the program counter address of a last transmitted program counter sync point and then transmits trace data in event offset format. If the first trace data following detection of corruption is a program counter sync point, then the trace transmits trace data in event offset format.

67. 发明授权

US07047270B2 Reporting a saturated counter value 有权
标题翻译：报告饱和计数器值
公开(公告)号：US07047270B2
公开(公告)日：2006-05-16
申请号：US10301897
申请日：2002-11-22
申请人： Manisha Agarwala , John M. Johnsen , Lewis Nardini
发明人： Manisha Agarwala , John M. Johnsen , Lewis Nardini
IPC分类号： G06F7/38
CPC分类号： G06F11/261
摘要： A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number. The counter indicates overflow when the overflow count is non-zero and saturates and stops counting at a maximum count when the overflow count reaches the second predetermined number. The counter can be read via a register read operation. The sum of the sum of the first predetermined number of bits and the second predetermined number of bits being an integral multiple of 8 bits.
摘要翻译：饱和计数将接收的事件信号计数到第一预定数量。溢出计数器计数溢出到第二预定数量。当溢出计数达到第二个预定数量时，计数器指示溢出计数不为零并饱和，并以最大计数停止计数。可以通过寄存器读取操作读取计数器。第一预定位数和第二预定位数之和为8位的整数倍的总和。

68. 发明授权

US5338983A Application specific exclusive of based logic module architecture for FPGAs 失效
标题翻译：专用于FPGA的基于逻辑模块架构的应用
公开(公告)号：US5338983A
公开(公告)日：1994-08-16
申请号：US166330
申请日：1993-12-10
申请人： Manisha Agarwala
发明人： Manisha Agarwala
IPC分类号： G06F7/00 , G06F7/50 , G06F7/501 , H03K19/173 , H03K19/177
CPC分类号： G06F7/501 , H03K19/1736 , G06F2207/4812
摘要： A logic module (20) includes five input terminals (a-e), two output terminals (F1, F2), and control logic (22, 24, 26, 28, 30, 32, 36) for selectively coupling one or more of the input terminals to one of the output terminals. First and second input terminals (a, b) are connected to inputs of a first XOR gate (22); a third input terminal (c) is connected to one input of a multiplexor (24) through an inverter (26); a fourth input terminal (d) is connected to the other input of the multiplexor (24) and to one input of a first NAND gate (28); and a fifth input terminal (e) is connected to one input of a second XOR gate (30) and to one input of a second NAND gate (32). The first XOR gate (22) has its output connected to the other input of the first NAND gate (28) and to the control input of the multiplexor (24). The output of the multiplexor (24) is connected to the other inputs of the second XOR gate (30) and second NAND gate (32). The outputs of the first and second NAND gates (28, 32) are connected to the inputs of a third NAND gate (36). The outputs of the third NAND gate (36) and second XOR gate (30) are the output terminals (F2, F1) of the logic module (10). The configuration of the logic module (20) permits implementation of adders and subtractors for DSPs with only one logic module.
摘要翻译：逻辑模块（20）包括五个输入端（ae），两个输出端（F1，F2）和控制逻辑（22,24,26,28,30,32,36），用于选择性地耦合一个或多个输入端子到其中一个输出端子。第一和第二输入端子（a，b）连接到第一异或门（22）的输入端; 第三输入端（c）通过反相器（26）连接到多路复用器（24）的一个输入端; 第四输入端（d）连接到多路复用器（24）的另一输入端和第一NAND门（28）的一个输入端; 和第五输入端（e）连接到第二异或门（30）的一个输入端和第二与非门（32）的一个输入端。第一异或门（22）的输出端连接到第一与非门（28）的另一个输入端和多路复用器（24）的控制输入端。多路复用器（24）的输出端连接到第二异或门（30）和第二与非门（32）的其它输入端。第一与非门（28,32）的输出端连接到第三与非门（36）的输入端。第三与非门（36）和第二异或门（30）的输出是逻辑模块（10）的输出端子（F2，F1）。逻辑模块（20）的配置允许仅使用一个逻辑模块来实现DSP的加法器和减法器。

69. 发明授权

US08832318B2 Dynamic data trace output scheme 有权
标题翻译：动态数据跟踪输出方案
公开(公告)号：US08832318B2
公开(公告)日：2014-09-09
申请号：US11563821
申请日：2006-11-28
申请人： Manisha Agarwala , Maria B. H. Gill , John M. Johnsen
发明人： Manisha Agarwala , Maria B. H. Gill , John M. Johnsen
IPC分类号： G06F15/16 , G06F11/36
CPC分类号： G06F11/3636 , G06F11/3656
摘要： Data streams are generated for tracing target processor activity. When multiple streams are on, they are written at different times into their individual FIFO. It is possible that for a specific stream, the length and fields of the data that should be exported vary. This invention is a scheme to send out only the relevant fields.
摘要翻译：生成跟踪目标处理器活动的数据流。当多个流打开时，它们会在不同的时间被写入其各自的FIFO。对于特定的流，可能导出的数据的长度和字段可能不同。本发明是仅发出相关领域的方案。

70. 发明授权

US08401835B2 Trigger ordering for trace streams when multiple triggers accumulate 有权
标题翻译：当多个触发器累积时，触发排序跟踪流
公开(公告)号：US08401835B2
公开(公告)日：2013-03-19
申请号：US10302083
申请日：2002-11-22
申请人： Manisha Agarwala , John M. Johnsen , Lewis Nardini
发明人： Manisha Agarwala , John M. Johnsen , Lewis Nardini
IPC分类号： G06F9/455 , G06F11/00
CPC分类号： G06F11/3636
摘要： In the case of tracing processor activity and generating data streams multiple triggers can be generated at the same time. The issue is further complicated in a protected pipeline where certain locations are considered as in illegal instruction boundary. During those cycles certain information is invalid and cannot be transmitted to the user. Thus a received trace trigger cannot begin. This invention resolves all ambiguities related to multiple triggers so that the user has a known predictable behavior based on the setup of the triggers.
摘要翻译：在跟踪处理器活动和生成数据流的情况下，可以同时生成多个触发器。这个问题在受保护的管道中进一步复杂化，其中某些位置被视为非法指令边界。在这些周期中，某些信息是无效的，不能发送给用户。因此，接收到的跟踪触发器不能开始。本发明解决了与多个触发相关的所有歧义，使得用户基于触发器的设置具有已知的可预测行为。

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