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61. 发明申请

US20150178203A1 OPTIMIZED WRITE ALLOCATION FOR TWO-LEVEL MEMORY 审中-公开
标题翻译：两级记忆的优化写入分配
公开(公告)号：US20150178203A1
公开(公告)日：2015-06-25
申请号：US14140256
申请日：2013-12-24
申请人： Marc Torrant , Jorge E. Parra , Blaise Fanning , Joydeep Ray
发明人： Marc Torrant , Jorge E. Parra , Blaise Fanning , Joydeep Ray
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/123
摘要： Systems and methods for write allocation by a two-level memory controller. An example processing system comprises: a processing core; a memory controller communicatively coupled to the processing core; and a system memory communicatively coupled to the memory controller, the system memory comprising a first level memory and a second level memory; wherein the memory controller is configured, responsive to determining that a memory block referenced by a memory write request is not present in the first level memory, to allocate a new first level memory block without retrieving the memory block referenced by the request from the second level memory, wherein the memory write request is represented by an overwrite type memory write request.
摘要翻译：由两级内存控制器进行写入分配的系统和方法。一个示例处理系统包括：处理核心; 通信地耦合到所述处理核心的存储器控制器; 以及系统存储器，其通信地耦合到所述存储器控制器，所述系统存储器包括第一级存储器和第二级存储器; 其中，所述存储器控制器被配置为响应于确定由所述存储器写请求引用的存储器块不存在于所述第一级存储器中，以分配新的第一级存储器块而不从所述第二级检索由所述请求引用的所述存储器块存储器，其中存储器写入请求由覆盖型存储器写入请求表示。

62. 发明申请

US20140297938A1 NON-VOLATILE RANDOM ACCESS MEMORY (NVRAM) AS A REPLACEMENT FOR TRADITIONAL MASS STORAGE 有权
标题翻译：非易失性随机存取存储器（NVRAM）作为传统存储的替代
公开(公告)号：US20140297938A1
公开(公告)日：2014-10-02
申请号：US13976362
申请日：2011-09-30
申请人： Leena K. Puthiyedath , Blaise Fanning , Tony Opferman , James B. Crossland
发明人： Leena K. Puthiyedath , Blaise Fanning , Tony Opferman , James B. Crossland
IPC分类号： G06F12/02
CPC分类号： G06F3/0679 , G06F3/061 , G06F3/0631 , G06F3/0643 , G06F3/0644 , G06F12/00 , G06F12/0238 , G06F12/0638 , G06F12/08 , G06F12/0804 , G06F12/0866 , G06F2212/1004 , G06F2212/1056 , G06F2212/2024 , G06F2212/214 , G06F2212/251 , G06F2212/7201
摘要： A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.
摘要翻译：在计算机系统中使用非易失性随机存取存储器（NVRAM）来在平台存储层级中执行多个角色，特别是替换可由I / O访问的传统大容量存储。计算机系统包括执行软件的处理器和耦合到处理器的存储器。存储器的至少一部分包括可由处理器进行字节可重写和字节可擦除的非易失性随机存取存储器（NVRAM）。该系统还包括耦合到NVRAM的存储器控制器，以响应于来自软件的访问大容量存储器的请求来执行存储器访问操作以访问NVRAM。

63. 发明申请

US20140258583A1 Providing Multiple Decode Options For A System-On-Chip (SoC) Fabric 审中-公开
标题翻译：为片上系统（SoC）提供多种解码选项
公开(公告)号：US20140258583A1
公开(公告)日：2014-09-11
申请号：US14209184
申请日：2014-03-13
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Robert P. Adler
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Robert P. Adler
IPC分类号： G06F13/364
CPC分类号： G06F13/364 , G06F13/28 , G06F13/385 , G06F13/4027 , G06F2213/0026
摘要： In one embodiment, a system-on-chip (SoC) can be configured to receive a request from a master agent in a fabric coupled to the master agent, send a show command grant to the master agent responsive to selection of the request by the fabric, receive a command portion of a transaction corresponding to the request in the fabric and determine a target agent to receive the transaction based on the command portion, and thereafter send a transaction grant to the master agent for the transaction. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，系统级芯片（SoC）可以被配置为在耦合到主代理的结构中接收来自主代理的请求，响应于所选择的请求向主代理发送显示命令授予接收与结构中的请求相对应的事务的命令部分，并且基于命令部分确定接收事务的目标代理，然后向事务的主代理发送事务授权。描述和要求保护其他实施例。

64. 发明申请

US20140258578A1 Supporting Multiple Channels Of A Single Interface 审中-公开
标题翻译：支持单个接口的多个通道
公开(公告)号：US20140258578A1
公开(公告)日：2014-09-11
申请号：US14209146
申请日：2014-03-13
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Rohit R. Verma
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Rohit R. Verma
IPC分类号： G06F13/364
CPC分类号： G06F13/364 , G06F9/44 , G06F13/362 , G06F15/16
摘要： In one embodiment, the present invention includes a method for receiving a request for a transaction from a first agent in a fabric and obtaining an address, a requester identifier, a tag, and a traffic class of the transaction, and determining a channel of a target agent to receive the transaction based on at least two of the address, the requester identifier, the tag, and the traffic class. Based on this channel determination, the transaction can be sent to the channel of the target agent. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从结构中的第一代理接收对交易的请求并获得交易的地址，请求者标识符，标签和业务类别的方法，以及确定基于至少两个地址，请求者标识符，标签和流量类来接收交易的目标代理。基于此通道确定，可以将事务发送到目标代理的通道。描述和要求保护其他实施例。

65. 发明申请

US20140240326A1 Method, Apparatus, System For Representing, Specifying And Using Deadlines 有权
标题翻译：方法，设备，代表，指定和使用期限的系统
公开(公告)号：US20140240326A1
公开(公告)日：2014-08-28
申请号：US13780117
申请日：2013-02-28
申请人： Daniel F. Cutter , Blaise Fanning , Ramadass Nagarajan , Ravishankar Iyer , Quang T. Le , Ravi Kolagotla , Ioannis T. Schoinas , Jose S. Niell
发明人： Daniel F. Cutter , Blaise Fanning , Ramadass Nagarajan , Ravishankar Iyer , Quang T. Le , Ravi Kolagotla , Ioannis T. Schoinas , Jose S. Niell
IPC分类号： G06F3/06
CPC分类号： G06F13/00 , G06F9/00 , G06F13/1626 , Y02D10/14
摘要： In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有相关联的顺序标识符和在存储器请求完成之前指示最大等待时间的最后期限值。响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。描述和要求保护其他实施例。

66. 发明申请

US20140201471A1 Arbitrating Memory Accesses Via A Shared Memory Fabric 有权
标题翻译：仲裁存储器通过共享存储器访问
公开(公告)号：US20140201471A1
公开(公告)日：2014-07-17
申请号：US13743795
申请日：2013-01-17
申请人： Daniel F. Cutter , Blaise Fanning , Ramadass Nagarajan , Jose S. Niell , Debra Bernstein , Deepak Limaye , Ioannis T. Schoinas , Ravishankar Iyer
发明人： Daniel F. Cutter , Blaise Fanning , Ramadass Nagarajan , Jose S. Niell , Debra Bernstein , Deepak Limaye , Ioannis T. Schoinas , Ravishankar Iyer
IPC分类号： G06F13/16
CPC分类号： G06F13/1663 , G06F13/1605 , G06F13/161 , G06F2212/1024 , G06F2213/0064 , Y02D10/14
摘要： In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有关联的最终期限值，以在完成存储器请求之前指示最大等待时间。响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。描述和要求保护其他实施例。

67. 发明申请

US20140185436A1 GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL 审中-公开
标题翻译：一般输入/输出结构，协议和相关方法实施流量控制
公开(公告)号：US20140185436A1
公开(公告)日：2014-07-03
申请号：US14145384
申请日：2013-12-31
申请人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
发明人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
IPC分类号： H04L12/801
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： A storage device is provided to maintain a value of flow control credits allocated for a device on a channel and flow control logic is provided to receive a flow control signal over a link of an interconnect, the flow control signal indicating flow control credits allocated for the device on the channel. The flow control logic is further to update the value of flow control credits based on activity of the device on the channel.
摘要翻译：提供存储装置以维持为信道上的设备分配的流量控制信用的值，并且提供流控制逻辑以通过互连的链路接收流控制信号，所述流控制信号指示为设备在通道上。流量控制逻辑还基于通道上的设备的活动来更新流量控制信用的值。

68. 发明申请

US20130138858A1 Providing A Sideband Message Interface For System On A Chip (SoC) 有权
公开(公告)号：US20130138858A1
公开(公告)日：2013-05-30
申请号：US13306244
申请日：2011-11-29
申请人： Robert P. Adler , Eran Tamari , Mikal C. Hunsaker , Sridhar Lakshmanamurthy , Michael T. Klinglesmith , Blaise Fanning
发明人： Robert P. Adler , Eran Tamari , Mikal C. Hunsaker , Sridhar Lakshmanamurthy , Michael T. Klinglesmith , Blaise Fanning
IPC分类号： G06F13/36
CPC分类号： G06F13/4221 , G06F13/366 , G06F13/4036
摘要： According to one embodiment, a system on a chip includes multiple agents each corresponding to an intellectual property (IP) logic and a fabric to couple the agents. The fabric can include a primary message interface and a sideband message interface. The fabric further includes one or more routers to provide out-of-band communications between the agents via this sideband message interface. To effect such communication, the router can perform a subset of ordering rules of a personal computer (PC)-based specification for sideband messages. Other embodiments are described and claimed.

69. 发明申请

US20130086288A1 Supporting Multiple Channels Of A Single Interface 有权
标题翻译：支持单个接口的多个通道
公开(公告)号：US20130086288A1
公开(公告)日：2013-04-04
申请号：US13248270
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Rohit R. Verma
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Rohit R. Verma
IPC分类号： G06F13/362
CPC分类号： G06F13/364 , G06F9/44 , G06F13/362 , G06F15/16
摘要： In one embodiment, the present invention includes a method for receiving a request for a transaction from a first agent in a fabric and obtaining an address, a requester identifier, a tag, and a traffic class of the transaction, and determining a channel of a target agent to receive the transaction based on at least two of the address, the requester identifier, the tag, and the traffic class. Based on this channel determination, the transaction can be sent to the channel of the target agent. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于从结构中的第一代理接收对交易的请求并获得交易的地址，请求者标识符，标签和业务类别的方法，以及确定基于至少两个地址，请求者标识符，标签和流量类来接收交易的目标代理。基于此通道确定，可以将事务发送到目标代理的通道。描述和要求保护其他实施例。

70. 发明申请

US20080159336A1 POWER CONTROL TECHNIQUES FOR BUS INTERFACES 审中-公开
标题翻译：总线接口功率控制技术
公开(公告)号：US20080159336A1
公开(公告)日：2008-07-03
申请号：US11618845
申请日：2006-12-31
申请人： Blaise Fanning
发明人： Blaise Fanning
IPC分类号： H04J3/00
CPC分类号： G06F13/4072 , G06F1/3203 , G06F1/3253 , Y02D10/151
摘要： Techniques are disclosed involving the transfer of signals across interconnection media. For instance, an apparatus may include a configuration module and a driver module. The configuration module may select one or more of multiple phase intervals within a time duration. This time duration may correspond to the time period length employed in a sequence of time periods. The driver module provides an interconnection medium with an output signal during one of the time periods. The output signal has an input signal level during the selected phase interval(s) of the period. During any remaining phase intervals of the time period, the driver module provides an alternate signal level.
摘要翻译：公开了涉及通过互连介质传送信号的技术。例如，设备可以包括配置模块和驱动器模块。配置模块可以在一段时间内选择多个相位间隔中的一个或多个。该持续时间可以对应于在一段时间段中使用的时间段长度。驱动器模块在一个时间段内提供具有输出信号的互连介质。输出信号在该周期的所选相位间隔期间具有输入信号电平。在该时间周期的任何剩余相位间隔期间，驱动器模块提供备用信号电平。

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