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61. 发明申请

US20120235242A1 Control of Local Environment for Polysilicon Conductors in Integrated Circuits 有权
标题翻译：集成电路中多晶硅导体的局部环境控制
公开(公告)号：US20120235242A1
公开(公告)日：2012-09-20
申请号：US13049862
申请日：2011-03-16
申请人： James Walter Blatchford, JR. , Yong Seok Choi
发明人： James Walter Blatchford, JR. , Yong Seok Choi
IPC分类号： H01L27/04 , H01L21/336
CPC分类号： H01L29/66484 , H01L21/28123 , H01L21/823828 , H01L27/0207 , H01L29/78
摘要： A method of fabricating gate level electrodes and interconnects in an integrated circuit, and an integrated circuit so fabricated, with improved process margin for the gate level interconnects of a width near the critical dimension. Off-axis illumination, as used in the photolithography of deep sub-micron critical dimension, is facilitated by the patterned features having a preferred orientation in a common direction, with a pitch constrained to within a relatively narrow range. Interconnects in that same gate level, for example “field poly” interconnects, that run parallel to an array of gate elements are placed within a specified distance range from the ends of the gate elements, or at a distance sufficient to allow sub-resolution assist features.
摘要翻译：一种在集成电路中制造栅极电极和互连的方法，以及如此制造的集成电路，其具有改进的临界尺寸附近的栅极级互连的工艺裕度。在深亚微米临界尺寸的光刻中使用的离轴照明通过具有在相同方向上具有优选取向的图案化特征促进，其间距限制在相对较窄的范围内。在与栅极元件阵列平行的同一栅极级别（例如，“多晶”互连）的互连被放置在从栅极元件的端部指定的距离范围内，或者距离足以允许次级分辨率辅助特征。

62. 发明申请

US20120162004A1 APPARATUS AND METHOD FOR ESTIMATING DIRECTION OF ARRIVAL OF SIGNAL IN COMMUNICATION SYSTEM 审中-公开
标题翻译：用于估计通信系统中信号到达方向的装置和方法
公开(公告)号：US20120162004A1
公开(公告)日：2012-06-28
申请号：US13334969
申请日：2011-12-22
申请人： Sang-Tae KIM , Gwangmoon Park , Seong-Yun Lee , Haeng-Sook Ro , Mi-kyung Suk , Yong-Seok Choi
发明人： Sang-Tae KIM , Gwangmoon Park , Seong-Yun Lee , Haeng-Sook Ro , Mi-kyung Suk , Yong-Seok Choi
IPC分类号： G01S13/02
CPC分类号： G01S3/74
摘要： Disclosed is an apparatus and method for estimating a direction of arrival (DOA) of a signal, which improves DOA estimation performance of a reception signal having a low signal to interference and noise ratio (SINR) in a communication system. In the method, a received signal is converted into a signal of a frequency region. A noise signal is separated from the signal converted into the signal of the frequency region. A noise region is filtered by setting an occupied bandwidth from the signal having the noise signal separated therefrom. A DOA of the signal obtained through the filtering of the noise region is estimated.
摘要翻译：公开了一种用于估计信号的到达方向（DOA）的装置和方法，其提高了通信系统中具有低信噪比（SINR）的接收信号的DOA估计性能。在该方法中，接收信号被转换为频率区域的信号。噪声信号与被转换成频率区域的信号的信号分离。通过从具有与其分离的噪声信号的信号设置占用带宽来对噪声区域进行滤波。估计通过噪声区域的滤波获得的信号的DOA。

63. 发明授权

US08189777B2 Apparatus and method for driving display panel 有权
标题翻译：用于驱动显示面板的装置和方法
公开(公告)号：US08189777B2
公开(公告)日：2012-05-29
申请号：US11984385
申请日：2007-11-16
申请人： Yong-Seok Choi
发明人： Yong-Seok Choi
IPC分类号： H04L29/06
CPC分类号： G09C5/00 , H04K1/00 , H04L2209/30
摘要： A display panel driver includes: an encryption unit configured to receive pixel data of unit pixels from an image data source, generate an encryption key by comparing an odd-numbered pixel data with a subsequent even-numbered pixel data, and assign a reference value corresponding to the encryption key; and a decryption unit configured to receive the encryption key and the reference value, compare the encryption key with a decryption key, and restore the odd-numbered pixel data and the even-numbered pixel data by using the reference value according to the comparison result.
摘要翻译：显示面板驱动器包括：加密单元，被配置为从图像数据源接收单位像素的像素数据，通过将奇数像素数据与随后的偶数像素数据进行比较来生成加密密钥，并且分配对应的参考值加密密钥; 以及解密单元，被配置为接收加密密钥和参考值，将加密密钥与解密密钥进行比较，并且通过使用根据比较结果的参考值来恢复奇数像素数据和偶数像素数据。

64. 发明申请

US20120038384A1 PROBE BOARD AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：探针板及其制造方法
公开(公告)号：US20120038384A1
公开(公告)日：2012-02-16
申请号：US13013335
申请日：2011-01-25
申请人： Yong Seok CHOI
发明人： Yong Seok CHOI
IPC分类号： G01R31/00 , H05K13/00
CPC分类号： G01R3/00 , Y10T29/49124
摘要： There are provided a probe board and a method of manufacturing the same. The probe board includes a ceramic substrate having an uneven portion in one surface thereof, one or more electrode pads placed on the uneven portion, and a buffer portion placed along an outer circumferential surface of each of the electrode pads, the buffer portion being formed by melting the ceramic substrate.
摘要翻译：提供了探针板及其制造方法。探针板包括其一个表面中具有不平坦部分的陶瓷基板，设置在不平坦部分上的一个或多个电极焊盘以及沿每个电极焊盘的外周表面放置的缓冲部分，缓冲部分由熔化陶瓷基板。

65. 发明申请

US20120026204A1 THREE-DIMENSIONAL DISPLAY AND DRIVING METHOD THEREOF 有权
标题翻译：三维显示及其驱动方法
公开(公告)号：US20120026204A1
公开(公告)日：2012-02-02
申请号：US13007327
申请日：2011-01-14
申请人： Byung-Ki Chun , Jong-Woong Park , Joo-Hyung Lee , Geun-Young Jeong , Yong-Seok Choi
发明人： Byung-Ki Chun , Jong-Woong Park , Joo-Hyung Lee , Geun-Young Jeong , Yong-Seok Choi
IPC分类号： G09G5/10
CPC分类号： G09G3/3648 , G09G3/003 , G09G3/3406 , G09G3/3607 , G09G2320/0646 , G09G2340/06
摘要： A three-dimensional (3D) display is disclosed. One aspect includes: a display unit including a plurality of pixels and a slit barrier selectively shielding light irradiated from the display unit. The display unit additionally includes a controller controlling the turn-on and turn-off of the slit barrier and generating a first back light compensation signal compensating the reduction of the luminance of the display unit when the slit barrier is turned off and a second back light compensation signal compensating the reduction of the luminance of the display when the slit barrier is turned on to compensate the luminance reduction by the slit barrier. According to at least one aspect of the 3D display using a slit barrier scheme, it is possible to minimize the deterioration of luminance by a slit barrier.
摘要翻译：公开了三维（3D）显示。一个方面包括：包括多个像素的显示单元和选择性地屏蔽从显示单元照射的光的狭缝屏障。显示单元还包括控制狭缝屏障的接通和关断的控制器，并且产生第一背光补偿信号，该第一背光补偿信号补偿当狭缝屏障被切断时显示单元的亮度降低，而第二背光补偿信号补偿当狭缝势垒被打开时显示器的亮度的降低以补偿狭缝屏障的亮度降低。根据使用狭缝屏障方案的3D显示器的至少一个方面，可以通过狭缝屏障来最小化亮度的劣化。

66. 发明授权

US08008200B2 Poison-free and low ULK damage integration scheme for damascene interconnects 有权
标题翻译：无毒低密度ULK损伤集成方案，用于大马士革互连
公开(公告)号：US08008200B2
公开(公告)日：2011-08-30
申请号：US13023315
申请日：2011-02-08
申请人： Ping Jiang , William W. Dostalik , Yong Seok Choi
发明人： Ping Jiang , William W. Dostalik , Yong Seok Choi
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76811 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a dual damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using a tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.
摘要翻译：公开了一种形成双镶嵌结构的方法。在超低k膜上沉积下介电硬掩模层和上绝缘硬掩模层。在上部硬掩模层中形成第一通孔。接下来，使用三层抗蚀剂方案形成第一沟槽。最后，同时形成完整通孔和全沟槽。可以在超低k层中使用可选的蚀刻停止层来控制沟槽深度。

67. 发明申请

US20110143533A1 POISON-FREE AND LOW ULK DAMAGE INTEGRATION SCHEME FOR DAMASCENE INTERCONNECTS 有权
标题翻译：无连接和低ULK损伤集成方案用于大型互连
公开(公告)号：US20110143533A1
公开(公告)日：2011-06-16
申请号：US13023315
申请日：2011-02-08
申请人： Ping Jiang , William W. Dostalik , Yong Seok Choi
发明人： Ping Jiang , William W. Dostalik , Yong Seok Choi
IPC分类号： H01L21/768
CPC分类号： H01L21/76811 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a dual damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using a tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.
摘要翻译：公开了一种形成双镶嵌结构的方法。在超低k膜上沉积下介电硬掩模层和上绝缘硬掩模层。在上部硬掩模层中形成第一通孔。接下来，使用三层抗蚀剂方案形成第一沟槽。最后，同时形成完整通孔和全沟槽。可以在超低k层中使用可选的蚀刻停止层来控制沟槽深度。

68. 发明授权

US07824829B2 Method of monitoring focus in lithographic processes 有权
标题翻译：监测光刻过程中焦点的方法
公开(公告)号：US07824829B2
公开(公告)日：2010-11-02
申请号：US11769436
申请日：2007-06-27
申请人： Yong Seok Choi
发明人： Yong Seok Choi
IPC分类号： G03F9/00 , G03C5/00
CPC分类号： G03F7/70433 , G03F1/44 , G03F7/70625 , G03F7/70641
摘要： The present disclosure is directed to a method for monitoring focus of a photolithography system. The method comprises providing a substrate and depositing a photoresist layer on the substrate. At least one photomask is provided comprising one or more forbidden pitch photomask patterns formed thereon. The forbidden pitch patterns are imaged in the photoresist layer by exposing the photoresist layer to radiation through the at least one photomask. The imaged forbidden pitch patterns are developed in the photoresist. Focus error information regarding the imaging process can be determined using the developed forbidden pitch patterns.
摘要翻译：本公开涉及一种用于监测光刻系统的焦点的方法。该方法包括提供衬底并在衬底上沉积光致抗蚀剂层。提供至少一个光掩模，其包括形成在其上的一个或多个禁止间距光掩模图案。通过将光致抗蚀剂层暴露于通过至少一个光掩模的辐射，将禁止的间距图案成像在光致抗蚀剂层中。成像的禁止间距图案在光致抗蚀剂中显影。可以使用开发的禁止俯仰图案来确定关于成像过程的聚焦误差信息。

69. 发明授权

US07755099B2 Light emitting device package 有权
标题翻译：发光装置封装
公开(公告)号：US07755099B2
公开(公告)日：2010-07-13
申请号：US12146292
申请日：2008-06-25
申请人： Yong Seok Choi
发明人： Yong Seok Choi
IPC分类号： H01L33/00
CPC分类号： H01L33/483 , H01L24/97 , H01L33/60 , H01L33/62 , H01L2224/97 , H01L2924/12041 , H01L2224/48091 , H01L2924/00014 , H01L2224/85 , H01L2924/00
摘要： Provided is a light emitting device package. The light emitting device package comprises a base substrate, a frame, and a light emitting device. The base substrate comprises a plurality of electrode pads. The frame is formed of silicon, attached on the base substrate, and has an opening. The light emitting device is electrically connected to the electrode pad in the opening.
摘要翻译：提供了一种发光器件封装。发光器件封装包括基底，框架和发光器件。基底包括多个电极垫。框架由硅形成，附着在基底基板上，并具有开口。发光器件电连接到开口中的电极焊盘。

70. 发明授权

US07755098B2 Zinc oxide light emitting diode 失效
标题翻译：氧化锌发光二极管
公开(公告)号：US07755098B2
公开(公告)日：2010-07-13
申请号：US12419706
申请日：2009-04-07
申请人： Seong-Ju Park , Dae-Kue Hwang , Min-Ki Kwon , Min-Suk Oh , Yong-Seok Choi
发明人： Seong-Ju Park , Dae-Kue Hwang , Min-Ki Kwon , Min-Suk Oh , Yong-Seok Choi
IPC分类号： H01L33/00
CPC分类号： H01L33/28 , H01L33/02
摘要： Provided is a zinc oxide light emitting diode having improved optical characteristics. The zinc oxide light emitting diode includes an n-type semiconductor layer, a zinc oxide active layer formed on the n-type semiconductor layer, a p-type semiconductor layer formed on the active layer, an anode in electrical contact with the p-type semiconductor layer, a cathode in electrical contact with the n-type semiconductor layer, and a surface plasmon layer disposed between the n-type semiconductor layer and the active layer or between the active layer and the p-type semiconductor layer. Since the surface plasmon layer is formed between the n-type semiconductor layer and the active layer or between the active layer and the p-type semiconductor layer, the light emitting diode is not affected by an increase in resistance due to reduction of the thickness of the p-type semiconductor layer, and has improved optical characteristics due to a resonance phenomenon between the surface plasmon layer and the active layer.
摘要翻译：提供了具有改善的光学特性的氧化锌发光二极管。氧化锌发光二极管包括n型半导体层，形成在n型半导体层上的氧化锌有源层，形成在有源层上的p型半导体层，与p型电接触的阳极半导体层，与n型半导体层电接触的阴极以及设置在n型半导体层与有源层之间或者在有源层与p型半导体层之间的表面等离子体质子层。由于表面等离子体膜层形成在n型半导体层和有源层之间或有源层与p型半导体层之间，所以发光二极管不受由于厚度的降低导致的电阻增加的影响 p型半导体层，并且由于表面等离子体激元层和活性层之间的共振现象而具有改善的光学特性。

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