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    • 61. 发明授权
    • ESD protection circuit for mixed-voltage I/O by using stacked NMOS transistors with substrate triggering technique
    • US06657835B2
    • 2003-12-02
    • US09874996
    • 2001-06-07
    • Ming-Dou KerChien-Hui ChuangWen-Yu Lo
    • Ming-Dou KerChien-Hui ChuangWen-Yu Lo
    • H02H900
    • H01L27/0266H01L2924/0002H01L2924/00
    • An ESD protection circuit for Mixed-Voltage I/O by using stacked NMOS transistors with substrate triggering technique is disclosed. The ESD protection circuit contains a set of stacked NMOS transistors with a first NMOS transistor and a second NMOS transistor, a parasitic lateral bipolar transistor, a substrate current generating circuit, and a parasitic substrate resistor. The drain of the first NMOS transistor connects to an I/O pad. The gate of the first NMOS transistor connects to a first working voltage. The source of the first NMOS transistor connects to the drain of the second NMOS transistor. The gate of the second NMOS transistor connects to an internal circuit. The source of the second NMOS transistor connects to a second working voltage. The collector of the parasitic lateral bipolar transistor connects to the drain of the first NMOS transistor and its emitter connects to the source of the second NMOS transistor. A first terminal of the substrate current generating circuit connects to the I/O pad, a second terminal connects to the second working voltage, and a third terminal connects to the substrate of the lateral bipolar transistor, so that a triggering current is sent out of the third terminal when the voltage at the I/O pad is over a predetermined value. One end of the parasitic substrate resistor connects to the base of the bipolar transistor and the other end connects to the second working voltage, using the triggering current to generate a bias for the bipolar transistor. During ESD-stress condition, such ESD protection circuit can be quickly triggered on to discharge ESD current. During IC normal circuit operating condition, such ESD protection circuit is kept off.
    • 62. 发明授权
    • N-type buried layer drive-in recipe to reduce pits over buried antimony layer
    • N型掩埋层驱动配方,减少埋在锑层上的坑
    • US06444551B1
    • 2002-09-03
    • US09910202
    • 2001-07-23
    • Wen-Yu KuFang-Cheng LuTing-Pang LiCheng-Chung Wang
    • Wen-Yu KuFang-Cheng LuTing-Pang LiCheng-Chung Wang
    • H01L21425
    • H01L21/2253H01L21/74
    • A method of driving-in antimony into a wafer, including the following steps. A wafer is loaded into an annealing furnace/tool. The wafer having an area of implanted antimony ions. The wafer is annealed a first time at a first temperature in the presence of only a first nitrogen gas flow rate. The wafer is ramped-down from the first temperature to a second temperature in the presence of only an oxygen gas flow rate. The wafer is maintained in the presence of the of oxygen gas flow rate at the second temperature. The wafer is ramped-up from the second temperature to a third temperature in the presence of only the oxygen gas flow rate. The wafer is annealed a second time at the third temperature in the presence of only a second nitrogen gas flow rate to drive-in the antimony ions within the area of implanted antimony.
    • 一种将锑引入晶片的方法,包括以下步骤。 将晶片装载到退火炉/工具中。 该晶片具有注入的锑离子的面积。 在仅有第一氮气流量存在的情况下,在第一温度下第一次对晶片进行退火。 在只有氧气流量存在的情况下,晶片从第一温度下降到第二温度。 在第二温度下,在存在氧气流速的情况下保持晶片。 在仅存在氧气流速的情况下,晶片从第二温度升高到第三温度。 在仅第二氮气流速存在的情况下,在第三温度下第二次退火晶片,以驱动在注入锑的区域内的锑离子。
    • 65. 发明授权
    • Packing box
    • 包装盒
    • US5860589A
    • 1999-01-19
    • US736667
    • 1996-10-25
    • Wen Yu Hsu
    • Wen Yu Hsu
    • B65D5/42
    • B65D5/4237B65D5/4204Y10S229/921
    • A packing box made from a patterned cardboard having a bottom panel, a top panel, two side panels, a front panel, and a rear panel, wherein a rectangular bottom frame is extended from one long side of the bottom panel remote from the front panel, having two adhesion flaps respectively extended from one long side and one short side thereof and adhered to the bottom panel at an outer side, defining with the bottom panel a bottom window and an insertion hole at one side for the insertion of a card into the bottom window; a rectangular top frame is extended from one long side of one side panel remote from the bottom panel, having two adhesion flaps respectively extended from one long side and one short side thereof and adhered to the top panel at an outer side, defining with the top panel a top window and an insertion hole at one side for the insertion of a card into the top window.
    • 由具有底板,顶板,两个侧板,前面板和后面板的图案化纸板制成的包装盒,其中矩形底框架从底板的远离前面板的一个长边延伸 具有分别从一个长边和一个短边延伸的两个粘合翼片,并且在外侧粘附到底板,其中底板限定了底部窗口和一侧的插入孔以将卡插入到 底窗; 矩形顶框架从一个侧面板的远离底板的一个长边延伸,具有分别从一个长边和一个短边延伸的两个粘合片,并在外侧粘附到顶板, 一个顶部窗口和一侧的插入孔,用于将卡插入顶部窗口。
    • 66. 发明授权
    • Mobile type of automatic identification system for a car plate
    • 移动式汽车板自动识别系统
    • US5425108A
    • 1995-06-13
    • US124445
    • 1993-09-22
    • Chung-Mu HwangWen-Yu ChenShyh-Yeong Shu
    • Chung-Mu HwangWen-Yu ChenShyh-Yeong Shu
    • G06K7/14G06K9/34G06K9/00
    • G06K7/1482G06K7/14G06K9/34G06K2209/01
    • An automatic identification system for a car-plate which comprises a photographing apparatus and an image-processing CPU. The system disclosed in the present invention can be mounted in a car for automatically identifying a car-plate that is under a still or moving condition. The photographing apparatus is used for taking the image of a car-plate, and the image is then transmitted into the image-processing CPU, which accurately extracts the characters of a car-plate using a "Fuzzy inference" technique, and identifies the characters through a character structure analysis neural network. With the automatic identification system of the present invention, an incorrect identification can be avoided in the event the image of a car-plate is blurred, and the characters is deformed or smeared.
    • 一种用于车板的自动识别系统,包括摄影装置和图像处理CPU。 本发明公开的系统可以安装在汽车中,用于自动识别处于静止或移动状态的轿厢板。 拍摄装置用于拍摄汽车板的图像,然后将图像发送到图像处理CPU中,图像处理CPU使用“模糊推理”技术精确地提取汽车板的字符,并且识别字符 通过字符结构分析神经网络。 利用本发明的自动识别系统,在汽车板的图像模糊,字符变形或模糊的情况下,可以避免错误的识别。
    • 67. 发明申请
    • DIRECT CURRENT SMELTING ELECTRIC FURNACE
    • US20210025654A1
    • 2021-01-28
    • US16968622
    • 2019-02-01
    • Wen YU
    • Wen YU
    • F27D11/08G01R31/42F27D3/18
    • A direct current smelting electric furnace includes a rectifying control circuit, a rectifying power supply device, a short network device, a multi-load layout device including multiple electrodes, and an electric furnace body. The rectifying power supply device includes at least two double-circuit direct current power supply packs. Four output terminals of each double-circuit direct current power supply pack are connected to three electrodes in the multi-load layout device by the short network device to constitute two current circuits by an electric furnace weld pool load. Each electrode in the multi-load layout device is connected to homo-polar output terminals of a three-phase negative semi-cycle rectifying output circuit and a three-phase positive semi-cycle rectifying output circuit, separately. The rectifying power supply device-includes multiple output current circuits. The number of output current circuits of the rectifying power supply device is the same as the number of electrodes in the multi-load layout device.