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61. 发明申请

US20080132089A1 METHODS FOR DISCRETIZED PROCESSING AND PROCESS SEQUENCE INTEGRATION OF REGIONS OF A SUBSTRATE 有权
公开(公告)号：US20080132089A1
公开(公告)日：2008-06-05
申请号：US12028666
申请日：2008-02-08
申请人： Tony P. Chiang , David E. Lazovsky , Thomas R. Boussie , Alexander Gorer
发明人： Tony P. Chiang , David E. Lazovsky , Thomas R. Boussie , Alexander Gorer
IPC分类号： H01L21/00
CPC分类号： H01L21/67011 , C23C14/54 , C23C16/4412 , C23C16/45544 , C23C16/4557 , C23C16/45578 , C23C16/4583 , C23C16/46 , C23C16/52 , H01J37/32449 , H01J37/32513 , H01J37/32724 , H01J2237/166 , H01J2237/20228 , H01J2237/20235 , H01L21/6715 , H01L21/76849 , H01L22/20 , H01L2924/0002 , Y10S438/907 , Y10S438/913 , Y10T137/8593 , H01L2924/00
摘要： The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

62. 发明申请

US20070267631A1 System and Method for Increasing Productivity of Combinatorial Screening 有权
标题翻译：提高组合筛选生产力的系统和方法
公开(公告)号：US20070267631A1
公开(公告)日：2007-11-22
申请号：US11419174
申请日：2006-05-18
申请人： Kurt H. Weiner , Tony P. Chiang , Gustavo A. Pinto
发明人： Kurt H. Weiner , Tony P. Chiang , Gustavo A. Pinto
IPC分类号： H01L23/58
CPC分类号： H01L22/10 , H01L21/67005 , H01L22/34
摘要： The present invention provides systems and methods for simultaneous, parallel and/or rapid serial testing of material parameters or other parameters of the result of a process. The testing is typically used for screening different methods or materials to select those methods or materials with desired properties. A reactor structure used to form the materials may consist of an array of small isolated reaction chambers that overlie the substrate so that the substrate forms a bottom surface of each isolated reaction chamber. Test structures are formed on the substrate, where the location of each test structure corresponds to an isolated reaction chamber area of the reaction structure. Test structures are used to measure certain parameters, such as by probing contact pads for each test structure, or such testing may be performed in-situ during processing.
摘要翻译：本发明提供用于同时，并行和/或快速连续测试材料参数或过程结果的其它参数的系统和方法。测试通常用于筛选不同的方法或材料以选择具有所需性质的那些方法或材料。用于形成材料的反应器结构可以由覆盖在基板上的小的分离的反应室的阵列组成，使得基板形成每个分离的反应室的底表面。在基板上形成测试结构，其中每个测试结构的位置对应于反应结构的分离的反应室区域。测试结构用于测量某些参数，例如通过探测每个测试结构的接触垫，或者可以在处理期间原位进行这种测试。

63. 发明授权

US06569501B2 Sequential method for depositing a film by modulated ion-induced atomic layer deposition (MII-ALD) 有权
公开(公告)号：US06569501B2
公开(公告)日：2003-05-27
申请号：US10137851
申请日：2002-05-03
申请人： Tony P. Chiang , Karl F. Leeser
发明人： Tony P. Chiang , Karl F. Leeser
IPC分类号： H05H100
CPC分类号： C23C16/45538 , C23C16/45525 , C23C16/45544 , C23C16/46 , C23C16/463 , C23C16/466 , C23C16/481 , C23C16/483 , H01L21/28562 , H01L21/76843 , H01L21/76871
摘要： The present invention relates to an enhanced sequential atomic layer deposition (ALD) technique suitable for deposition of barrier layers, adhesion layers, seed layers, low dielectric constant (low-k) films, high dielectric constant (high-k) films, and other conductive, semi-conductive, and non-conductive films. This is accomplished by 1) providing a non-thermal or non-pyrolytic means of triggering the deposition reaction; 2) providing a means of depositing a purer film of higher density at lower temperatures; and, 3) providing a faster and more efficient means of modulating the deposition sequence and hence the overall process rate resulting in an improved deposition method.

64. 发明授权

US09255329B2 Modulated ion-induced atomic layer deposition (MII-ALD) 有权
标题翻译：调制离子诱导原子层沉积（MII-ALD）
公开(公告)号：US09255329B2
公开(公告)日：2016-02-09
申请号：US12510922
申请日：2009-07-28
申请人： Tony P. Chiang , Karl Leeser
发明人： Tony P. Chiang , Karl Leeser
IPC分类号： H05H1/46 , C23C16/06 , C23C16/455 , C23C16/22 , C23C16/46 , H01L21/285 , H01L21/768
CPC分类号： C23C16/45536 , C23C16/06 , C23C16/22 , C23C16/45534 , C23C16/45538 , C23C16/463 , H01L21/28562 , H01L21/76843
摘要： The present invention relates to a cyclic deposition process suitable for depositing an elemental film. The process employs an enhanced atomic layer deposition technique.
摘要翻译：本发明涉及适于沉积元素膜的循环沉积工艺。该方法采用增强的原子层沉积技术。

65. 发明授权

US09175382B2 High metal ionization sputter gun 有权
标题翻译：高金属电离溅射枪
公开(公告)号：US09175382B2
公开(公告)日：2015-11-03
申请号：US13281316
申请日：2011-10-25
申请人： Hong Sheng Yang , Tony P. Chiang , Kent Riley Child , Chi-I Lang , ShouQian Shao
发明人： Hong Sheng Yang , Tony P. Chiang , Kent Riley Child , Chi-I Lang , ShouQian Shao
IPC分类号： C23C14/34 , H01J37/34 , C23C14/35
CPC分类号： C23C14/345 , C23C14/3485 , C23C14/352 , H01J37/3402 , H01J37/3405 , H01J37/3458 , H01J37/3467
摘要： In one aspect of the invention, a process chamber is provided. The chamber includes a plurality of sputter guns with a target affixed to one end of each of the sputter guns. Each of the plurality of sputter guns is coupled to a first power source. The first power source is operable to provide a pulsed power supply to each of the plurality of sputter guns. The pulsed power supply has a duty cycle that is less than 30%. A substrate support disposed at a distance from the plurality of sputter guns is included. The substrate support is coupled to a second power source. The second power source is operable to bias a substrate disposed on the substrate support, wherein the duty cycle of the second power source is synchronized with a duty cycle of the first power source. A method of performing a deposition process is also included.
摘要翻译：在本发明的一个方面，提供一种处理室。该腔室包括多个溅射枪，其中目标物固定在每个溅射枪的一端。多个溅射枪中的每一个耦合到第一电源。第一电源可操作以向多个溅射枪中的每一个提供脉冲电源。脉冲电源的占空比小于30％。包括设置在距离多个溅射枪一定距离的衬底支撑件。衬底支撑件耦合到第二电源。第二电源可操作以偏置设置在衬底支撑件上的衬底，其中第二电源的占空比与第一电源的占空比同步。还包括执行沉积工艺的方法。

66. 发明授权

US08853099B2 Nonvolatile resistive memory element with a metal nitride containing switching layer 有权
标题翻译：具有含有金属氮化物的开关层的非易失性电阻性存储元件
公开(公告)号：US08853099B2
公开(公告)日：2014-10-07
申请号：US13328423
申请日：2011-12-16
申请人： Yun Wang , Tony P. Chiang , Imran Hashim , Tim Minvielle , Takeshi Yamaguchi
发明人： Yun Wang , Tony P. Chiang , Imran Hashim , Tim Minvielle , Takeshi Yamaguchi
IPC分类号： H01L21/31
CPC分类号： H01L45/145 , B82Y10/00 , H01L27/2409 , H01L27/2463 , H01L45/10 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A nonvolatile resistive memory element has a novel variable resistance layer that includes a metal nitride, a metal oxide-nitride, a two-metal oxide-nitride, or a multilayer stack thereof. One method of forming the novel variable resistance layer comprises an interlayer deposition procedure, in which metal oxide layers are interspersed with metal nitride layers and then converted into a substantially homogeneous layer by an anneal process. Another method of forming the novel variable resistance layer comprises an intralayer deposition procedure, in which various ALD processes are sequentially interleaved to form a metal oxide-nitride layer. Alternatively, a metal oxide is deposited, nitridized, and annealed to form the variable resistance layer or a metal nitride is deposited, oxidized, and annealed to form the variable resistance layer.
摘要翻译：非易失性电阻存储元件具有新颖的可变电阻层，其包括金属氮化物，金属氧化物氮化物，二金属氧化物氮化物或其多层叠层。形成新颖的可变电阻层的一种方法包括层间沉积程序，其中金属氧化物层散布有金属氮化物层，然后通过退火工艺转变成基本均匀的层。形成新型可变电阻层的另一种方法包括层间沉积程序，其中各种ALD工艺顺序交错以形成金属氧化物 - 氮化物层。或者，金属氧化物被沉积，氮化和退火以形成可变电阻层，或者金属氮化物被沉积，氧化和退火以形成可变电阻层。

67. 发明授权

US08803124B2 Creating an embedded reram memory from a high-K metal gate transistor structure 有权
标题翻译：从高K金属栅极晶体管结构创建嵌入式reram存储器
公开(公告)号：US08803124B2
公开(公告)日：2014-08-12
申请号：US13407997
申请日：2012-02-29
申请人： Dipankar Pramanik , Tony P. Chiang , David Lazovsky
发明人： Dipankar Pramanik , Tony P. Chiang , David Lazovsky
IPC分类号： H01L47/00
CPC分类号： H01L45/1658 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1683
摘要： An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.
摘要翻译：本发明的实施例提出了一种嵌入式电阻式存储单元，其包括沉积层的第一堆叠，沉积层的第二堆叠，设置在第一堆叠的第一部分下方的第一电极和设置在第二堆叠下的第二电极的第二电极第一堆叠的部分并且从第一堆叠的第二部分下方延伸到第二堆叠下方。第二电极设置在嵌入式电阻式存储单元内靠近第一电极。第一堆沉积层包括介电层，设置在电介质层上方的高k电介质层和设置在高k电介质层上方的金属层。第二层沉积层包括与包含在第一堆叠中的高k电介质层同时形成的高k电介质层和设置在高k电介质层上方的金属层。

68. 发明授权

US08726838B2 Combinatorial plasma enhanced deposition and etch techniques 有权
标题翻译：组合等离子体增强沉积和蚀刻技术
公开(公告)号：US08726838B2
公开(公告)日：2014-05-20
申请号：US12963995
申请日：2010-12-09
申请人： Sunil Shanker , Tony P. Chiang , Chi-I Lang
发明人： Sunil Shanker , Tony P. Chiang , Chi-I Lang
IPC分类号： C23C16/50 , C23C16/509 , H01L21/3065 , C23C16/455 , C23C16/02 , C23C16/458 , H01L21/67 , H01J37/32
CPC分类号： H01L21/02274 , C23C16/0227 , C23C16/44 , C23C16/45523 , C23C16/45525 , C23C16/45536 , C23C16/45548 , C23C16/45565 , C23C16/45574 , C23C16/4586 , C23C16/509 , C23C16/5096 , H01J37/32091 , H01J37/3244 , H01J37/32532 , H01J37/32541 , H01J37/32568 , H01J37/32715 , H01J37/32779 , H01L21/3065 , H01L21/67069
摘要： According to various embodiments of the disclosure, an apparatus and method for enhanced deposition and etch techniques is described, including a pedestal, the pedestal having at least two electrodes embedded in the pedestal, a showerhead above the pedestal, a plasma gas source connected to the showerhead, wherein the showerhead is configured to deliver plasma gas to a processing region between the showerhead and the substrate and a power source operably connected to the showerhead and the at least two electrodes with plasma being substantially contained in an area which corresponds with one electrode of the at least two electrodes.
摘要翻译：根据本公开的各种实施例，描述了一种用于增强沉积和蚀刻技术的装置和方法，包括基座，具有至少两个嵌入基座的电极的基座，基座上方的喷头，连接到基座的等离子体气体源淋浴头，其中所述喷头被构造成将等离子体气体输送到所述喷头和所述基板之间的处理区域，以及电源，其可操作地连接到所述喷头和所述至少两个电极，其中等离子体基本上包含在对应于所述至少两个电极。

69. 发明授权

US08697606B2 Methods for discretized processing and process sequence integration of regions of a substrate 有权
标题翻译：离散化处理方法和基板区域的工艺顺序整合
公开(公告)号：US08697606B2
公开(公告)日：2014-04-15
申请号：US13311855
申请日：2011-12-06
申请人： Tony P. Chiang , David E. Lazovsky , Thomas R. Boussie , Alexander Gorer
发明人： Tony P. Chiang , David E. Lazovsky , Thomas R. Boussie , Alexander Gorer
IPC分类号： C40B50/00
CPC分类号： H01L21/67011 , C23C14/54 , C23C16/4412 , C23C16/45544 , C23C16/4557 , C23C16/45578 , C23C16/4583 , C23C16/46 , C23C16/52 , H01J37/32449 , H01J37/32513 , H01J37/32724 , H01J2237/166 , H01J2237/20228 , H01J2237/20235 , H01L21/6715 , H01L21/76849 , H01L22/20 , H01L2924/0002 , Y10S438/907 , Y10S438/913 , Y10T137/8593 , H01L2924/00
摘要： The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.
摘要翻译：本发明提供了用于基板区域的离散化，组合处理的方法和系统，例如用于集成电路制造中使用的新材料，工艺和工艺顺序集成方案的发现，实现，优化和鉴定。通过将材料输送到衬底或修改衬底的区域来处理其上具有差分处理区域阵列的衬底。

70. 发明授权

US08614787B2 High throughput quantum efficiency combinatorial characterization tool and method for combinatorial solar test substrates 失效
公开(公告)号：US08614787B2
公开(公告)日：2013-12-24
申请号：US12952855
申请日：2010-11-23
申请人： Yun Wang , Tony P. Chiang , Chi-I Lang
发明人： Yun Wang , Tony P. Chiang , Chi-I Lang
IPC分类号： G01N21/00
CPC分类号： G01R31/26 , G01N21/55 , G01R31/2607 , H02S50/10
摘要： Simultaneous measurement of an internal quantum efficiency and an external quantum efficiency of a solar cell using an emitter that emits light; a three-way beam splitter that splits the light into solar cell light and reference light, wherein the solar cell light strikes the solar cell; a reference detector that detects the reference light; a reflectance detector that detects reflectance light, wherein the reflectance light comprises a portion of the solar cell light reflected off the solar cell; a source meter operatively coupled to the solar cell; a multiplexer operatively coupled to the solar cell, the reference detector, and the reflectance detector; and a computing device that simultaneously computes the internal quantum efficiency and the external quantum efficiency of the solar cell.

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