专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20130052825A1 SEMICONDUCTOR PROCESS 有权
标题翻译：半导体工艺
公开(公告)号：US20130052825A1
公开(公告)日：2013-02-28
申请号：US13220692
申请日：2011-08-30
申请人： Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chun-Wei Hsu , Yen-Ming Chen , Chih-Hsun Lin , Chang-Hung Kung
发明人： Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chun-Wei Hsu , Yen-Ming Chen , Chih-Hsun Lin , Chang-Hung Kung
IPC分类号： H01L21/306
CPC分类号： H01L21/3212 , H01L21/3105 , H01L21/31051 , H01L21/31053 , H01L21/7684 , H01L21/823835 , H01L29/665
摘要： A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.
摘要翻译：半导体工艺包括以下步骤。第一栅极结构和第二栅极结构形成在基板上，其中第一栅极结构的顶部包括盖层，使得第一栅极结构的垂直高度高于第二栅极结构的垂直高度。在基板上形成介电层。执行第一化学机械抛光工艺以暴露盖层的顶表面。执行第二化学机械抛光工艺以暴露第二栅极结构的顶表面，或执行蚀刻工艺以去除位于第二栅极结构上的介电层。然后执行第二化学机械抛光工艺以除去盖层。

62. 发明申请

US20130037886A1 SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130037886A1
公开(公告)日：2013-02-14
申请号：US13206533
申请日：2011-08-10
申请人： Teng-Chun Tsai , Chun-Yuan Wu , Chih-Chien Liu , Chin-Cheng Chien , Chin-Fu Lin
发明人： Teng-Chun Tsai , Chun-Yuan Wu , Chih-Chien Liu , Chin-Cheng Chien , Chin-Fu Lin
IPC分类号： H01L27/092 , H01L21/782 , H01L27/12 , H01L21/8238
CPC分类号： H01L21/845 , H01L21/823821 , H01L27/0924 , H01L27/1211 , H01L29/1054 , H01L29/165
摘要： A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.
摘要翻译：半导体器件包括半导体衬底，至少第一鳍结构，至少第二鳍结构，第一栅极，第二栅极，第一源极/漏极区域和第二源极/漏极区域。半导体衬底至少具有第一有源区以配置第一鳍结构和至少第二有源区以配置第二鳍结构。与第一/第二栅极部分重叠的第一/第二鳍结构具有第一/第二应力，第一应力和第二应力彼此不同。第一/第二源极/漏极区域设置在第一/第二栅极的两侧的第一/第二鳍结构中。

63. 发明申请

US20120220134A1 METHOD FOR CLEARING NATIVE OXIDE 有权
标题翻译：用于清除原料氧化物的方法
公开(公告)号：US20120220134A1
公开(公告)日：2012-08-30
申请号：US13468042
申请日：2012-05-10
申请人： Yen-Chu Chen , Teng-Chun Tsai , Chien-Chung Huang , Keng-Jen Liu
发明人： Yen-Chu Chen , Teng-Chun Tsai , Chien-Chung Huang , Keng-Jen Liu
IPC分类号： H01L21/461 , B08B5/00
CPC分类号： H01L21/3065 , H01L21/02057 , H01L21/02063
摘要： A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.
摘要翻译：描述了清除天然氧化物的方法。提供了一种衬底，包括其中形成有自然氧化物层的暴露部分。使用三氟化氮（NF 3）和氨（NH 3）作为反应气体对基板进行清除处理，其中NF 3的体积流量大于NH 3的体积流量。

64. 发明申请

US20110065245A1 METHOD FOR FABRICATING MOS TRANSISTOR 审中-公开
标题翻译：制造MOS晶体管的方法
公开(公告)号：US20110065245A1
公开(公告)日：2011-03-17
申请号：US12558565
申请日：2009-09-13
申请人： Jei-Ming Chen , Kuo-Chih Lai , Teng-Chun Tsai , Hsiu-Lien Liao
发明人： Jei-Ming Chen , Kuo-Chih Lai , Teng-Chun Tsai , Hsiu-Lien Liao
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6659 , H01L29/7843 , H01L29/7847
摘要： A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate and a source/drain region in the semiconductor substrate adjacent to two sides of the gate structure; covering a stress layer on the gate structure and the source/drain region; etching away the stress layer to form a plurality of openings with larger top and smaller bottom to expose surface of the gate structure and the source/drain region; forming a metal layer in the openings; and using the stress layer as a salicide block to react the metal layer with the gate structure and the source/drain region for forming a plurality of silicide layers.
摘要翻译：公开了一种用于制造金属氧化物半导体（MOS）晶体管的方法。该方法包括以下步骤：提供半导体衬底; 在所述半导体衬底上形成栅极结构，在所述半导体衬底中与所述栅极结构的两侧相邻的源/漏区; 覆盖栅极结构和源极/漏极区域上的应力层; 蚀刻掉应力层以形成具有较大顶部和较小底部的多个开口以暴露栅极结构和源极/漏极区域的表面; 在开口中形成金属层; 并且使用应力层作为自对准硅化物块使金属层与栅极结构和源极/漏极区域反应以形成多个硅化物层。

65. 发明申请

US20100001317A1 CMOS TRANSISTOR AND THE METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译： CMOS晶体管及其制造方法
公开(公告)号：US20100001317A1
公开(公告)日：2010-01-07
申请号：US12168062
申请日：2008-07-03
申请人： Yi-Wei Chen , Teng-Chun Tsai , Chien-Chung Huang , Jei-Ming Chen , Tsai-Fu Hsiao
发明人： Yi-Wei Chen , Teng-Chun Tsai , Chien-Chung Huang , Jei-Ming Chen , Tsai-Fu Hsiao
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L29/165 , H01L29/66628 , H01L29/7843
摘要： A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.
摘要翻译：公开了一种CMOS晶体管及其制造方法。提供了至少具有PMOS晶体管和NMOS晶体管的半导体衬底。 PMOS晶体管的源极/漏极包括SiGe外延层。执行碳注入工艺以在PMOS晶体管的源极/漏极的顶部部分中形成碳掺杂层。在源极/漏极上形成硅化物层。在PMOS晶体管和NMOS晶体管上形成CESL。碳掺杂层的形成能够防止Ge扩散。

66. 发明授权

US07642166B2 Method of forming metal-oxide-semiconductor transistors 有权
标题翻译：形成金属氧化物半导体晶体管的方法
公开(公告)号：US07642166B2
公开(公告)日：2010-01-05
申请号：US12265736
申请日：2008-11-06
申请人： Kun-Hsien Lee , Cheng-Tung Huang , Wen-Han Hung , Shyh-Fann Ting , Li-Shian Jeng , Tzyy-Ming Cheng , Neng-Kuo Chen , Shao-Ta Hsu , Teng-Chun Tsai , Chien-Chung Huang
发明人： Kun-Hsien Lee , Cheng-Tung Huang , Wen-Han Hung , Shyh-Fann Ting , Li-Shian Jeng , Tzyy-Ming Cheng , Neng-Kuo Chen , Shao-Ta Hsu , Teng-Chun Tsai , Chien-Chung Huang
IPC分类号： H01L213/8234
CPC分类号： H01L21/823807 , H01L21/823835 , H01L21/82385 , H01L21/823864 , H01L29/6653 , H01L29/6656 , H01L29/7843
摘要： A method of manufacturing a MOS transistor device is provided. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.
摘要翻译：提供一种制造MOS晶体管器件的方法。首先，准备具有栅极结构的半导体基板。栅极结构在侧壁上具有两个侧壁和衬垫。随后，在半导体衬底上形成应力覆盖层，并覆盖栅极结构和衬垫。接下来，执行激活处理。此外，将应力覆盖层蚀刻成为自对准硅化物块。之后，进行自对准处理以在未被应力覆盖层覆盖的区域上形成硅化物层。

67. 发明授权

US07544603B2 Method of fabricating silicon nitride layer and method of fabricating semiconductor device 有权
标题翻译：制造氮化硅层的方法和制造半导体器件的方法
公开(公告)号：US07544603B2
公开(公告)日：2009-06-09
申请号：US11233831
申请日：2005-09-22
申请人： Neng-Kuo Chen , Teng-Chun Tsai , Hsiu-Lien Liao
发明人： Neng-Kuo Chen , Teng-Chun Tsai , Hsiu-Lien Liao
IPC分类号： H01L21/20
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6659 , H01L29/7843
摘要： A method of fabricating a silicon nitride layer is described. First, a substrate is provided. Then, a silicon nitride layer is formed on the substrate. The silicon nitride layer is UV-cured in an atmosphere lower than the standard atmospheric pressure. Through the UV curing treatment, the tensile stress of the silicon nitride layer is increased.
摘要翻译：描述了制造氮化硅层的方法。首先，提供基板。然后，在基板上形成氮化硅层。氮化硅层在低于标准大气压的气氛中UV固化。通过UV固化处理，氮化硅层的拉伸应力增加。

68. 发明申请

US20090104773A1 METHOD OF FORMING CONTACT 有权
标题翻译：形成联系方法
公开(公告)号：US20090104773A1
公开(公告)日：2009-04-23
申请号：US12345670
申请日：2008-12-30
申请人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang
发明人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang
IPC分类号： H01L21/768
CPC分类号： H01L21/76801 , H01L21/76837 , H01L29/78
摘要： A substrate having at least two metal oxide semiconductor devices of a same conductive type and a gap formed between the two devices is provided. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate, filling the gap. An etching back process is then performed to remove a portion of the stress material layer inside the gap. A second stress layer and a dielectric layer are sequentially formed on the first stress layer. The first stress layer and the second stress layer provide a same type of stress. A portion of the second stress layer is removed to form a contact opening. A second conductive layer is filled into the contact opening to form a contact.
摘要翻译：提供了具有至少两个相同导电类型的金属氧化物半导体器件和在两个器件之间形成的间隙的衬底。第一应力层形成在衬底上以覆盖金属氧化物半导体器件和衬底，填补间隙。然后执行回蚀处理以去除间隙内部的应力材料层的一部分。第一应力层和电介质层依次形成在第一应力层上。第一应力层和第二应力层提供相同类型的应力。去除第二应力层的一部分以形成接触开口。将第二导电层填充到接触开口中以形成接触。

69. 发明申请

US20090068805A1 METHOD OF FORMING METAL-OXIDE-SEMICONDUCTOR TRANSISTORS 有权
标题翻译：形成金属氧化物半导体晶体管的方法
公开(公告)号：US20090068805A1
公开(公告)日：2009-03-12
申请号：US12265736
申请日：2008-11-06
申请人： Kun-Hsien Lee , Cheng-Tung Huang , Wen-Han Hung , Shyh-Fann Ting , Li-Shian Jeng , Tzyy-Ming Cheng , Neng-Kuo Chen , Shao-Ta Hsu , Teng-Chun Tsai , Chien-Chung Huang
发明人： Kun-Hsien Lee , Cheng-Tung Huang , Wen-Han Hung , Shyh-Fann Ting , Li-Shian Jeng , Tzyy-Ming Cheng , Neng-Kuo Chen , Shao-Ta Hsu , Teng-Chun Tsai , Chien-Chung Huang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823835 , H01L21/82385 , H01L21/823864 , H01L29/6653 , H01L29/6656 , H01L29/7843
摘要： A method of manufacturing a MOS transistor device is provided. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.
摘要翻译：提供一种制造MOS晶体管器件的方法。首先，准备具有栅极结构的半导体基板。栅极结构在侧壁上具有两个侧壁和衬垫。随后，在半导体衬底上形成应力覆盖层，并覆盖栅极结构和衬垫。接下来，执行激活处理。此外，将应力覆盖层蚀刻成为自对准硅化物块。之后，进行自对准处理以在未被应力覆盖层覆盖的区域上形成硅化物层。

70. 发明申请

US20080305600A1 METHOD AND APPARATUS FOR FABRICATING HIGH TENSILE STRESS FILM 有权
标题翻译：用于制备高拉应力膜的方法和装置
公开(公告)号：US20080305600A1
公开(公告)日：2008-12-11
申请号：US11758623
申请日：2007-06-05
申请人： Hsiu-Lien Liao , Neng-Kuo Chen , Teng-Chun Tsai , Yi-Wei Chen
发明人： Hsiu-Lien Liao , Neng-Kuo Chen , Teng-Chun Tsai , Yi-Wei Chen
IPC分类号： H01L21/336 , H01J37/08
CPC分类号： H01L21/324 , H01L29/665 , H01L29/66575 , H01L29/78 , H01L29/7843
摘要： A method and an apparatus for fabricating a high tensile stress film includes providing a substrate, forming a poly stressor on the substrate, and performing an ultra violet rapid thermal process (UVRTP) for curing the poly stressor and adjusting its tensile stress status, thus the poly stressor serves as a high tensile stress film. Due to a combination of energy from photons and heat, the tensile stress status of the high tensile stress film is adjusted in a relatively shorter process period or under a relatively lower temperature.
摘要翻译：用于制造高拉伸应力膜的方法和设备包括提供基板，在基板上形成多应力器，并且执行紫外线快速热处理（UVRTP），用于固化聚应力器并调整其拉伸应力状态，因此多应力器作为高拉伸应力膜。由于来自光子和热的能量的组合，高拉伸应力膜的拉伸应力状态在相对较短的工艺周期或相对较低的温度下调节。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式