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61. 发明授权

US11347396B2 Clock mode determination in a memory system 有权
公开(公告)号：US11347396B2
公开(公告)日：2022-05-31
申请号：US16950204
申请日：2020-11-17
申请人： Mosaid Technologies Incorporated
发明人： Peter B. Gillingham , Graham Allan
IPC分类号： G11C8/00 , G06F3/06 , G06F13/16 , G11C7/10 , G11C7/22 , G11C16/10 , G11C16/28 , G11C16/32 , G11C16/04 , G11C14/00 , H03K5/00
摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

62. 再颁专利

USRE49018E1 Charge pump for PLL/DLL 有权
公开(公告)号：USRE49018E1
公开(公告)日：2022-04-05
申请号：US16407380
申请日：2019-05-09
申请人： Mosaid Technologies Incorporated
发明人： Dieter Haerle
IPC分类号： H03L7/089 , H03L7/081
摘要： A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.

63. 发明申请

US20210408301A1 NAND FLASH MEMORY WITH VERTICAL CELL STACK STRUCTURE AND METHOD FOR MANUFACTURING SAME 有权
公开(公告)号：US20210408301A1
公开(公告)日：2021-12-30
申请号：US17369007
申请日：2021-07-07
申请人： Mosaid Technologies Incorporated
发明人： Hyoung Seub Rhie
IPC分类号： H01L29/792 , H01L29/66 , G11C16/04 , H01L27/11573 , H01L27/11582 , G11C11/56
摘要： Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.

64. 发明授权

US09117527B2 Non-volatile memory device having configurable page size 有权
标题翻译：具有可配置页面大小的非易失性存储器件
公开(公告)号：US09117527B2
公开(公告)日：2015-08-25
申请号：US14158116
申请日：2014-01-17
申请人： MOSAID TECHNOLOGIES INCORPORATED
发明人： Jin-Ki Kim
IPC分类号： G11C16/04 , G11C16/08 , G11C8/08 , G11C8/10 , G11C16/10
CPC分类号： G11C16/08 , G11C8/08 , G11C8/10 , G11C15/046 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/26
摘要： A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.
摘要翻译：具有至少一个存储体的闪速存储器件，其中每个存储体具有可独立配置的页面大小。每个存储体包括至少两个具有对应页面缓冲器的存储器平面，其中响应于配置数据和地址数据，同时选择性地访问存储器层的任何数量和组合。在上电时，可以将组态数据加载到存储设备中，以进行存储体的静态页面配置，或者可以通过每个命令接收配置数据以允许存储体的动态页面配置。通过选择性地调整存储体的页面大小，相应地调整块大小。

65. 发明授权

US08855277B2 Telephone outlet for implementing a local area network over telephone lines and a local area network using such outlets 有权
标题翻译：通过电话线实现局域网的电话插座和使用这种网点的局域网
公开(公告)号：US08855277B2
公开(公告)日：2014-10-07
申请号：US13751825
申请日：2013-01-28
申请人： MOSAID Technologies Incorporated
发明人： Yehuda Binder
IPC分类号： H04M11/00 , H04M11/06 , H04M7/00 , H04L12/28
CPC分类号： H04M7/0003 , H04L12/2803 , H04L12/2838 , H04L2012/2843 , H04L2012/2845 , H04L2012/285 , H04M11/062
摘要： An outlet for coupling at least one data unit to digital data carried over wiring that simultaneously carry a packet-based serial digital data signal and a power signal over the same conductors. The outlet includes: a wiring connector for connecting to the wiring; a transceiver coupled to the wiring connector for transmitting and receiving packet-based serial digital data over the wiring; a LAN connector coupled to the transceiver for bi-directional packet-based data communication with at least one data unit; a bridge or a router coupled between the transceiver and the LAN connector for passing data bi-directionally between the at least one data unit and the wiring; and a single enclosure housing the above-mentioned components. The enclosure is mountable into a standard wall outlet receptacle or wall outlet opening, and the transceiver and the bridge or router are coupled to the wiring connector to be powered from the power signal.
摘要翻译：用于将至少一个数据单元耦合到通过布线承载的数字数据的插座，其同时携带基于分组的串行数字数据信号和通过相同导体的功率信号。插座包括：用于连接到接线的接线连接器; 耦合到布线连接器的收发器，用于通过布线发送和接收基于分组的串行数字数据; 耦合到收发器的LAN连接器，用于与至少一个数据单元的双向分组数据通信; 耦合在所述收发器和所述LAN连接器之间的桥或路由器，用于在所述至少一个数据单元和所述布线之间双向传递数据; 以及容纳上述部件的单个外壳。外壳可安装到标准的墙壁插座或墙壁出口开口中，收发器和桥接器或路由器通过电源信号耦合到接线连接器供电。

66. 发明授权

US08817779B2 Telephone communication system and method over local area network wiring 有权
标题翻译：电话通信系统和方法通过局域网布线
公开(公告)号：US08817779B2
公开(公告)日：2014-08-26
申请号：US13956933
申请日：2013-08-01
申请人： MOSAID Technologies Incorporated
发明人： Yehuda Binder
IPC分类号： H04L5/20 , H04M11/06 , H04B3/54 , H04L12/66
CPC分类号： H04L5/20 , H04B3/542 , H04L12/66 , H04L2012/6421 , H04L2012/6424 , H04L2012/644 , H04M11/062 , H04M11/066 , Y10S439/95 , Y10T307/297
摘要： A device for enabling a local area network wiring structure to simultaneously carry digital data and analog telephone signals on the same transmission medium. It is particularly applicable to a network in star topology, in which remote data units (e.g. personal computers) are each connected to a hub through a cable comprising at least two pairs of conductors, providing a data communication path in each direction. Modules at each end of the cable provide a phantom path for telephony (voice band) signals between a telephone near the data set and a PBX, through both conductor pairs in a phantom circuit arrangement. All such communication paths function simultaneously and without mutual interference. The modules comprise simple and inexpensive passive circuit components.
摘要翻译：一种用于使局域网布线结构能够在相同传输介质上携带数字数据和模拟电话信号的装置。特别适用于星型拓扑网络，其中远程数据单元（例如，个人计算机）各自通过包括至少两对导体的电缆连接到集线器，从而在每个方向上提供数据通信路径。电缆每端的模块通过虚拟电路布置中的两个导体对提供了数据集附近的电话和PBX之间的电话（语音频带）信号的幻像路径。所有这些通信路径同时工作，没有相互干扰。这些模块包括简单而廉价的无源电路组件。

67. 发明授权

US08767430B2 Configurable module and memory subsystem 有权
标题翻译：可配置模块和内存子系统
公开(公告)号：US08767430B2
公开(公告)日：2014-07-01
申请号：US13957713
申请日：2013-08-02
申请人： MOSAID Technologies Incorporated
发明人： Peter Gillingham , Roland Schuetz
IPC分类号： G11C5/02 , G11C5/00 , G11C5/06 , G11C8/00
CPC分类号： G11C5/025 , G06F13/1684 , G06F13/4022 , G06F13/4243 , G11C16/04
摘要： A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.
摘要翻译：可配置存储器子系统包括具有电路板的存储器模块，该电路板具有安装在其上的第一和第二存储器容纳装置（MCD）对。每个MCD对具有与第二MCD通信的第一MCD。每个MCD都有一个输入端口，一个输出端口和一个与桥连通的存储器。响应于命令，桥将数据分组的一部分中的至少一个从输入端口传送到输出端口或存储器，或者将存储器分组的一部分从存储器传送到输出端口。环回装置从第一MCD对接收命令和数据包，并将命令和数据包发送到第二MCD对。

68. 发明申请

US20140179059A1 PACKAGE-LEVEL INTEGRATED CIRCUIT CONNECTION WITHOUT TOP METAL PADS OR BONDING WIRE 审中-公开
标题翻译：封装级集成电路连接，没有顶部金属焊盘或焊接线
公开(公告)号：US20140179059A1
公开(公告)日：2014-06-26
申请号：US14193436
申请日：2014-02-28
申请人： MOSAID Technologies Incorporated
发明人： Hong Beom PYEON
IPC分类号： H01L21/82 , H01L23/00
CPC分类号： H01L21/82 , H01L23/49805 , H01L24/05 , H01L24/24 , H01L24/37 , H01L24/40 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L2224/05599 , H01L2224/24145 , H01L2224/371 , H01L2224/37599 , H01L2225/06541 , H01L2225/06551 , H01L2924/00014 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H01L2924/351 , H01L2924/00 , H01L2224/84
摘要： An integrated circuit method is provided with package-level connectivity, between internal electronic circuitry thereof and contact points on a package substrate thereof, without requiring top metal pads or bonding wires.
摘要翻译：集成电路方法具有封装级连接性，其内部电子电路与其封装衬底上的接触点之间，而不需要顶部金属焊盘或接合线。

69. 发明申请

US20140151774A1 NAND FLASH MEMORY WITH VERTICAL CELL STACK STRUCTURE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：具有垂直单元堆叠结构的NAND闪存及其制造方法
公开(公告)号：US20140151774A1
公开(公告)日：2014-06-05
申请号：US13803085
申请日：2013-03-14
申请人： MOSAID TECHNOLOGIES INCORPORATED
发明人： Hyoung Seub Rhie
IPC分类号： H01L29/792 , H01L29/66
摘要： Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
摘要翻译：公开了一种制造具有垂直单元堆栈结构的闪速存储器的方法。该方法包括在具有离子注入阱的衬底的单元区域中形成源极线，并相对于源极线形成对准标记。对准标记形成在基板的单元区域外的基板中。在形成源极线之后，形成电池层叠层。在形成电池堆叠层之后，使用对准标记在相对于先前形成的源极线的位置处形成电池堆叠层中的电池柱，以正确地定位电池柱。

70. 发明申请

US20140133235A1 NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE 有权
标题翻译：具有可配置页尺寸的非易失性存储器件
公开(公告)号：US20140133235A1
公开(公告)日：2014-05-15
申请号：US14158116
申请日：2014-01-17
申请人： MOSAID TECHNOLOGIES INCORPORATED
发明人： Jin-Ki KIM
IPC分类号： G11C16/10
CPC分类号： G11C16/08 , G11C8/08 , G11C8/10 , G11C15/046 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/26
摘要： A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.
摘要翻译：具有至少一个存储体的闪速存储器件，其中每个存储体具有可独立配置的页面大小。每个存储体包括至少两个具有对应页面缓冲器的存储器平面，其中响应于配置数据和地址数据，同时选择性地访问存储器层的任何数量和组合。在上电时，可以将组态数据加载到存储设备中，以进行存储体的静态页面配置，或者可以通过每个命令接收配置数据以允许存储体的动态页面配置。通过选择性地调整存储体的页面大小，相应地调整块大小。

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