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61. 发明授权

US08722493B2 Logic transistor and non-volatile memory cell integration 有权
标题翻译：逻辑晶体管和非易失性存储单元集成
公开(公告)号：US08722493B2
公开(公告)日：2014-05-13
申请号：US13442142
申请日：2012-04-09
申请人： Mark D. Hall , Mehul D. Shroff
发明人： Mark D. Hall , Mehul D. Shroff
IPC分类号： H01L21/336
CPC分类号： H01L27/04 , H01L21/28273 , H01L27/11534 , H01L27/11575 , H01L29/42328 , H01L29/42332 , H01L29/66545 , H01L29/66825 , H01L29/7881
摘要： A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer and barrier layer are formed over the control gate. A sacrificial layer is formed over the barrier layer and planarized. A first patterned masking layer is formed over the sacrificial layer and control gate in the NVM region which defines a select gate location laterally adjacent the control gate in the NVM region. A second masking layer is formed in the logic region which defines a logic gate location. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location which exposes the barrier layer.
摘要翻译：图案化第一导电层和底层电荷存储层，以在NVM区域中形成控制栅极。第一介电层和阻挡层形成在控制栅上。在阻挡层上形成牺牲层并进行平坦化。在NVM区域中的牺牲层和控制栅极上形成第一图案化掩模层，其限定在NVM区域中横向邻近控制栅极的选择栅极位置。第二掩蔽层形成在限定逻辑门位置的逻辑区域中。去除牺牲层的暴露部分，使得第一部分保持在选择栅极位置。在第一部分上形成第二电介质层并将其平坦化以暴露第一部分。去除第一部分以在选择栅极位置处产生暴露阻挡层的开口。

62. 发明申请

US20140123085A1 SYSTEMS AND METHODS FOR DETERMINING AGING DAMAGE FOR SEMICONDUCTOR DEVICES 有权
标题翻译：用于确定半导体器件的老化损伤的系统和方法
公开(公告)号：US20140123085A1
公开(公告)日：2014-05-01
申请号：US13665256
申请日：2012-10-31
申请人： MEHUL D. SHROFF , PETER P. ABRAMOWITZ
发明人： MEHUL D. SHROFF , PETER P. ABRAMOWITZ
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5009 , G06F2217/76
摘要： A method includes generating a circuit design and executing a simulation of the circuit design at a plurality of time slices. Type 1 damage and type 2 damage are determined for each time slice. A total type 1 damage is provided as a sum of the type 1 damage for all of the slices in which type 1 damage is greater than type 2 damage. A total type 2 damage is similarly added for the slices where the type 2 damage is dominant. A type 1 aging effect is determined based on the total type 1 damage. A type 2 aging effect is determined based on the total type 2 damage. The type 1 aging effect is added to the type 2 aging effect to obtain a total aging effect. The circuit design is tested using the total aging effect to determine if the circuit design provides adequate lifetime performance.
摘要翻译：一种方法包括在多个时间片上产生电路设计并执行电路设计的仿真。确定每个时间片的1型伤害和2型伤害。对于类型1损伤大于2型伤害的所有切片，总共提供1型伤害的总和。对于类型2伤害占主导地位的切片，类似地总共增加了2型伤害。 1型老化效果基于1型总伤害确定。 2型老化效果根据2型总伤害确定。 1型老化效应被添加到2型老化效应中，以获得总老化效果。使用总衰老效应测试电路设计，以确定电路设计是否提供足够的寿命性能。

63. 发明授权

US08669158B2 Non-volatile memory (NVM) and logic integration 有权
标题翻译：非易失性存储器（NVM）和逻辑集成
公开(公告)号：US08669158B2
公开(公告)日：2014-03-11
申请号：US13780574
申请日：2013-02-28
申请人： Mark D. Hall , Frank K. Baker, Jr. , Mehul D. Shroff
发明人： Mark D. Hall , Frank K. Baker, Jr. , Mehul D. Shroff
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/11534 , H01L29/42328 , H01L29/42332 , H01L29/42348 , H01L29/4933 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66833 , H01L29/7881
摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer in an NVM region and a polysilicon dummy gate is formed over a second thermally-grown oxygen-containing layer in a logic region. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first and second thermally-grown oxygen-containing layers are formed. The second thermally-grown oxygen-containing layer and the dummy gate are replaced by a metal gate and a high-k dielectric. The logic transistor is protected while the NVM cell is then formed including forming a charge storage layer.
摘要翻译：形成NVM单元和逻辑晶体管的方法使用半导体衬底。在NVM区域中的第一热生长含氧层上形成NVM单元的多晶硅选择栅极，并且在逻辑区域中的第二热生长含氧层上形成多晶硅虚拟栅极。在形成第一和第二热生长含氧层之后形成源极/漏极，侧壁间隔物和逻辑晶体管的硅化物区域。第二热生长含氧层和虚拟栅极被金属栅极和高k电介质代替。保护逻辑晶体管，同时形成NVM单元，包括形成电荷存储层。

64. 发明申请

US20140038317A1 METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN METAL LAYERS 有权
标题翻译：在金属层之间形成电气连接的方法
公开(公告)号：US20140038317A1
公开(公告)日：2014-02-06
申请号：US13562534
申请日：2012-07-31
申请人： Edward O. Travis , Douglas M. Reber , Mehul D. Shroff
发明人： Edward O. Travis , Douglas M. Reber , Mehul D. Shroff
IPC分类号： H01L21/768
CPC分类号： H01L21/76816 , G06F17/5077 , H01L23/5226 , H01L29/41 , H01L2924/0002 , Y10T29/49124 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： A method forms an electrical connection between a first metal layer and a second metal layer. The second metal layer is above the first metal layer. A first via is formed between the first metal layer and the second metal layer. A first measure of a number of vacancies expected to reach the first via is obtained. A second via in at least one of the first metal layer and the second metal layer is formed if the measure of vacancies exceeds a first predetermined number.
摘要翻译：一种方法形成第一金属层和第二金属层之间的电连接。第二金属层在第一金属层之上。在第一金属层和第二金属层之间形成第一通孔。获得预计达到第一个通道的空缺数量的首要措施。如果空位的测量超过第一预定数量，则形成第一金属层和第二金属层中的至少一个的第二通孔。

65. 发明授权

US08633080B2 Methods of making multi-state non-volatile memory cells 有权
标题翻译：制造多态非易失性记忆体的方法
公开(公告)号：US08633080B2
公开(公告)日：2014-01-21
申请号：US13004985
申请日：2011-01-12
申请人： Mark D. Hall , Mehul D. Shroff
发明人： Mark D. Hall , Mehul D. Shroff
IPC分类号： H01L21/336
CPC分类号： H01L29/66833 , G11C11/5621 , G11C11/5671 , G11C16/0483 , G11C2216/06 , H01L21/02532 , H01L21/02595 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L27/11568 , H01L29/0653 , H01L29/42332 , H01L29/42348 , H01L29/51 , H01L29/6656 , H01L29/7887 , H01L29/7923
摘要： A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device.
摘要翻译：半导体器件包括半导体衬底中的具有在顶表面上具有第一电荷存储层的顶表面的区域。第一导电线在第一电荷存储层上。第二电荷存储层位于顶表面上。第二导电线在第二电荷存储层上。第三电荷存储层位于顶表面上。第三导电线在第三电荷存储层上。第四电荷存储层具有与第一导电线的第一侧壁相邻的第一侧和邻接第二导电线的第一侧壁的第二侧。第五电荷存储层具有邻接第二导电线的第二侧壁的第一侧和邻接第三导线的第一侧壁的第二侧。源极和漏极区域形成在半导体器件的任一侧上的衬底中。

66. 发明授权

US08624312B2 Semiconductor device structure as a capacitor 有权
标题翻译：半导体器件结构作为电容器
公开(公告)号：US08624312B2
公开(公告)日：2014-01-07
申请号：US13096543
申请日：2011-04-28
申请人： Mark D. Hall , Mehul D. Shroff
发明人： Mark D. Hall , Mehul D. Shroff
IPC分类号： H01L27/108
CPC分类号： H01L27/0805 , H01L23/5223 , H01L27/0629 , H01L27/0811 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure includes a conductive region; a first dielectric layer over the conductive region; a conductive material within the first dielectric layer, wherein the conductive material is on the conductive region and forms a first plate electrode of the capacitor structure; an insulating layer within the first dielectric layer and surrounding the conductive material; a first conductive layer within the first dielectric layer and surrounding the insulating layer, wherein the first conductive layer forms a second plate electrode of the capacitor structure; a second conductive layer laterally extending from the first conductive layer at a top surface of the first dielectric layer; a second dielectric layer over the first dielectric layer; and a third conductive layer within the second dielectric layer and on the conductive material.
摘要翻译：电容器结构包括导电区域; 在导电区域上的第一介电层; 在所述第一电介质层内的导电材料，其中所述导电材料在所述导电区域上并形成所述电容器结构的第一平板电极; 第一介电层内的绝缘层，并围绕导电材料; 所述第一导电层在所述第一介电层内并且包围所述绝缘层，其中所述第一导电层形成所述电容器结构的第二平板电极; 在第一介电层的顶表面处从第一导电层横向延伸的第二导电层; 第一电介质层上的第二电介质层; 以及在第二介电层内和导电材料上的第三导电层。

67. 发明授权

US08581390B2 Semiconductor device with heat dissipation 有权
标题翻译：半导体器件散热
公开(公告)号：US08581390B2
公开(公告)日：2013-11-12
申请号：US13442015
申请日：2012-04-09
申请人： Edward O. Travis , Douglas M. Reber , Mehul D. Shroff
发明人： Edward O. Travis , Douglas M. Reber , Mehul D. Shroff
IPC分类号： H01L23/34 , H01L23/10
CPC分类号： H01L23/3677 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/14164 , H01L2224/16225 , H01L2224/16227 , H01L2224/29015 , H01L2224/29082 , H01L2224/291 , H01L2224/29147 , H01L2224/30154 , H01L2224/30164 , H01L2224/30177 , H01L2224/73103 , H01L2224/73203 , H01L2224/81801 , H01L2224/83801 , H01L2224/9211 , H01L2225/06513 , H01L2225/06589 , H01L2924/00012 , H01L2924/00014 , H01L2924/014 , H01L2224/81 , H01L2224/83
摘要： A semiconductor assembly includes a semiconductor device and a connecting structure. The semiconductor device includes an interconnect region over a semiconductor substrate and a pillar layer having a plurality of pillar contacts on the interconnect region. The pillar layer also includes a plurality of radial heat conductors that have at least a portion overlying a heat source that is within and overlies the semiconductor substrate. Each radial heat conductor extends a length radially from the heat source that is at least twice as great as the diameter of the pillars. The connecting structure includes a connecting substrate that supports a first corresponding pillar contact that is in contact with a first pillar contact of the plurality of pillar contacts. The first connecting structure further includes a heat conductor, supported by the substrate, in contact with a first radial heat conductor of the plurality of radial heat conductors.
摘要翻译：半导体组件包括半导体器件和连接结构。半导体器件包括半导体衬底上的互连区域和在互连区域上具有多个柱状触点的柱层。柱层还包括多个径向热导体，其具有覆盖在半导体衬底内并覆盖半导体衬底的热源的至少一部分。每个径向导热体从热源的径向延伸至少两倍于柱的直径。连接结构包括支撑与多个柱接触件的第一柱接触件接触的第一对应的柱接触件的连接基板。所述第一连接结构还包括由所述基板支撑的与所述多个径向导热体的第一径向导热体接触的导热体。

68. 发明授权

US08569816B2 Isolated capacitors within shallow trench isolation 有权
标题翻译：浅沟槽隔离中的隔离电容
公开(公告)号：US08569816B2
公开(公告)日：2013-10-29
申请号：US13092037
申请日：2011-04-21
申请人： Mehul D. Shroff , Mark D. Hall
发明人： Mehul D. Shroff , Mark D. Hall
IPC分类号： H01L27/108 , H01L21/20
CPC分类号： H01L29/945 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer (10) below a trench opening, a capacitor dielectric layer (22) and a recessed top capacitor plate (28) that is covered by an STI region (30) and isolated from cross talk by a sidewall dielectric layer (23).
摘要翻译：半导体工艺和装置提供集成在集成电路中的浅沟槽隔离电容器结构，并且包括形成在沟槽开口下方的衬底层（10）中的底部电容器板，电容器电介质层（22）和凹陷顶部电容器板（28），其被STI区域（30）覆盖并且由侧壁电介质层（23）与串扰隔离。

69. 发明申请

US20130264633A1 LOGIC TRANSISTOR AND NON-VOLATILE MEMORY CELL INTEGRATION 有权
标题翻译：逻辑晶体管和非易失性存储器单元集成
公开(公告)号：US20130264633A1
公开(公告)日：2013-10-10
申请号：US13442142
申请日：2012-04-09
申请人： MARK D. HALL , MEHUL D. SHROFF
发明人： MARK D. HALL , MEHUL D. SHROFF
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/04 , H01L21/28273 , H01L27/11534 , H01L27/11575 , H01L29/42328 , H01L29/42332 , H01L29/66545 , H01L29/66825 , H01L29/7881
摘要： A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer and barrier layer are formed over the control gate. A sacrificial layer is formed over the barrier layer and planarized. A first patterned masking layer is formed over the sacrificial layer and control gate in the NVM region which defines a select gate location laterally adjacent the control gate in the NVM region. A second masking layer is formed in the logic region which defines a logic gate location. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location which exposes the barrier layer.
摘要翻译：图案化第一导电层和底层电荷存储层，以在NVM区域中形成控制栅极。第一介电层和阻挡层形成在控制栅上。在阻挡层上形成牺牲层并进行平坦化。在NVM区域中的牺牲层和控制栅极上形成第一图案化掩模层，其限定在NVM区域中横向邻近控制栅极的选择栅极位置。第二掩蔽层形成在限定逻辑门位置的逻辑区域中。去除牺牲层的暴露部分，使得第一部分保持在选择栅极位置。在第一部分上形成第二电介质层并将其平坦化以暴露第一部分。去除第一部分以在选择栅极位置处产生暴露阻挡层的开口。

70. 发明申请

US20130171786A1 NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION 有权
标题翻译：非易失性存储器（NVM）和逻辑集成
公开(公告)号：US20130171786A1
公开(公告)日：2013-07-04
申请号：US13441426
申请日：2012-04-06
申请人： Mehul D. Shroff , Mark D. Hall
发明人： Mehul D. Shroff , Mark D. Hall
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L27/11534 , H01L29/42328 , H01L29/42332 , H01L29/66545 , H01L29/66825 , H01L29/7881
摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over an NVM work function setting metal, the NVM work function setting metal is on a high-k dielectric, and a metal logic gate of a logic transistor is similarly formed over work function setting and high-k dielectric materials. The logic transistor is formed while portions of the metal select gate of the NVM cell are formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate.
摘要翻译：形成NVM单元和逻辑晶体管的方法使用半导体衬底。 NVM单元的金属选择栅极形成在NVM工作功能设定金属上，NVM工作功能设定金属位于高k电介质上，逻辑晶体管的金属逻辑门类似地形成工作功能设定和高电平 -k电介质材料。在形成NVM单元的金属选择栅极的部分的同时形成逻辑晶体管。在形成NVM单元的同时，保护逻辑晶体管，包括使用纳米晶体形成电荷存储区域，并在金属选择栅极的一部分上形成金属控制栅极以及在基板上的电荷存储区域的一部分。蚀刻电荷存储区域以与金属控制栅极对准。

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