专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US08185800B2 System for error control coding for memories of different types and associated methods 有权
标题翻译：用于不同类型和相关方法的存储器的错误控制编码系统
公开(公告)号：US08185800B2
公开(公告)日：2012-05-22
申请号：US12023408
申请日：2008-01-31
申请人： Paul W. Coteus , Luis A. Lastras-Montano , Warren Edward Maule , Barry M. Trager , Shmuel Winograd
发明人： Paul W. Coteus , Luis A. Lastras-Montano , Warren Edward Maule , Barry M. Trager , Shmuel Winograd
IPC分类号： G11C29/00
CPC分类号： H03M13/1545 , G06F11/1048 , H03M13/1515 , H03M13/154 , H03M13/35 , H03M13/353 , H03M13/3707 , H03M13/6511 , H03M13/6516
摘要： A system to improve error control coding. An example system includes memory chips of at least two different kinds. The system also includes error control encoder circuitry to substantially encode data for storage in any memory rank. The system further includes error control decoder circuitry to substantially decode encoded data received from any memory rank. The error decoder circuitry is comprised of a slow decoder and a fast decoder.
摘要翻译：一种改进错误控制编码的系统。示例系统包括至少两种不同类型的存储器芯片。该系统还包括错误控制编码器电路，用于基本上编码数据以存储在任何存储器级中。该系统还包括错误控制解码器电路，以基本上解码从任何存储器等级接收的编码数据。错误解码器电路由慢解码器和快速解码器组成。

62. 发明授权

US08181094B2 System to improve error correction using variable latency and associated methods 有权
标题翻译：使用可变延迟和相关方法改进纠错的系统
公开(公告)号：US08181094B2
公开(公告)日：2012-05-15
申请号：US12023546
申请日：2008-01-31
申请人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/00
CPC分类号： G06F11/1048
摘要： A system to improve error correction includes a fast decoder to process data packets until the fast decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated. The system also includes a slow decoder to correct the uncorrectable error in a data packet based upon the at least two data packets.
摘要翻译：改进纠错的系统包括处理数据分组的快速解码器，直到快速解码器在数据分组中发现不可校正的错误，在该时间点产生对至少两个数据分组的请求。该系统还包括缓慢解码器，用于基于至少两个数据分组校正数据分组中的不可校正错误。

63. 发明授权

US08176235B2 Non-volatile memories with enhanced write performance and endurance 有权
标题翻译：具有增强的写入性能和耐用性的非易失性存储器
公开(公告)号：US08176235B2
公开(公告)日：2012-05-08
申请号：US12631505
申请日：2009-12-04
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： Enhanced write performance for non-volatile memories including a memory system that includes a receiver for receiving a data rate of a data sequence to be written to a non-volatile flash memory device. The memory system also includes a physical page selector for selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, and for determining if the number of free bits in the invalid previously written memory page at the selected physical address is greater than or equal to the data rate. The memory system also includes a transmitter for outputting the selected physical address of the invalid previously written memory page, the outputting in response to the physical page selector determining that the number of free bits is greater than or equal to the data rate.
摘要翻译：对于非易失性存储器的增强的写入性能，包括存储器系统，该存储器系统包括用于接收要写入非易失性闪速存储器件的数据序列的数据速率的接收器。存储器系统还包括物理页面选择器，用于从位于非易失性存储器设备上的无效的先前写入的存储器页面的一组物理地址中选择无效的先前写入的存储器页面的物理地址，并且用于确定是否有空闲数量在所选物理地址处的无效的先前写入的存储器页中的位大于或等于数据速率。存储器系统还包括用于输出无效的先前写入的存储器页面的所选物理地址的发射器，响应于物理页选择器确定空闲位的数量大于或等于数据速率的输出。

64. 发明申请

US20110320914A1 ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM 有权
标题翻译：冗余存储系统中的错误校正和检测
公开(公告)号：US20110320914A1
公开(公告)日：2011-12-29
申请号：US12822503
申请日：2010-06-24
申请人： Luiz C. Alves , Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens
发明人： Luiz C. Alves , Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens
IPC分类号： G06F11/10
CPC分类号： G06F11/1004 , G06F11/108
摘要： Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices; a cyclical redundancy code (CRC) mechanism for detecting that one of the memory channels has failed, and for marking the memory channel as a failing memory channel; and an error correction code (ECC) mechanism. The ECC is configured for ignoring the marked memory channel and for detecting and correcting additional memory device failures on memory devices located on one or more of the other memory channels, thereby allowing the memory system to continue to run unimpaired in the presence of the memory channel failure.
摘要翻译：在包括存储器控制器的冗余存储器系统中的错误校正和检测; 与存储器控制器通信的多个存储器通道，存储器通道包括多个存储器件; 用于检测存储器通道之一的循环冗余码（CRC）机制已经失败，并用于将存储器通道标记为故障存储器通道; 和纠错码（ECC）机制。 ECC被配置为忽略标记的存储器通道并且用于检测和校正位于一个或多个其它存储器通道上的存储器设备上的附加存储器件故障，从而允许存储器系统在存在存储器通道的情况下继续运行不受损害失败。

65. 发明申请

US20110320911A1 Computer System and Method of Protection for the System's Marking Store 失效
标题翻译：计算机系统和系统标记商店的保护方法
公开(公告)号：US20110320911A1
公开(公告)日：2011-12-29
申请号：US12825521
申请日：2010-06-29
申请人： Richard E. Fry , Marc A. Gollub , Luis A. Lastras-Montano , Eric E. Retter , Kenneth L. Wright
发明人： Richard E. Fry , Marc A. Gollub , Luis A. Lastras-Montano , Eric E. Retter , Kenneth L. Wright
IPC分类号： H03M13/09
CPC分类号： G06F11/1048
摘要： A method and apparatus for controlling marking store updates in a central electronic complex with a plurality of core processors and eDRAM cache and interconnect bus to a service processor for loading memory controller firmware to dual-channel DDR3 memory controllers with an internal marking store. Loaded firmware of the memory controllers is responsible for tracking of ECC errors using a ECC decoder control whereby said marking store is written by a slow ECC decoder, and read by a fast ECC decoder for every read operation of said memory controllers to provide a blocking mechanism for notifying marking store firmware when the marking store has been updated and which guarantees that marking store firmware cannot write to the marking store until the marking store firmware has seen updates without causing the marking store hardware to time out.
摘要翻译：一种用于控制在具有多个核心处理器和eDRAM缓存和互连总线的中央电子复合体中将标记存储更新的方法和装置，用于将服务处理器用于使用内部标记存储器将存储器控制器固件加载到双通道DDR3存储器控制器。存储器控制器的加载固件负责使用ECC解码器控制来跟踪ECC错误，由此所述标记存储器由慢ECC解码器写入，并且由快速ECC解码器读取，用于所述存储器控制器的每次读取操作，以提供阻塞机制用于在更新标记存储时通知标记存储固件，并确保标记存储固件无法写入标记存储，直到标记存储固件看到更新，而不会导致标记存储硬件超时。

66. 发明申请

US20110320869A1 HOMOGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM 有权
标题翻译：在冗余存储系统中均衡恢复
公开(公告)号：US20110320869A1
公开(公告)日：2011-12-29
申请号：US12822964
申请日：2010-06-24
申请人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
发明人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
IPC分类号： G06F11/07 , G06F11/14
CPC分类号： G06F11/1666 , G06F11/1044 , G06F11/108 , G06F11/141 , G06F11/1604 , G06F11/20 , G06F11/2007 , G06F2211/1088
摘要： Providing homogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for blocking off new operations from starting on the memory channels, for completing any pending operations on the memory channels, for performing a recovery operation on the memory channels and for starting the new operations on at least a first subset of the memory channels. The memory system is capable of operating with the first subset of the memory channels.
摘要翻译：在包括存储器控制器，与存储器控制器通信的多个存储器通道，用于检测故障存储器通道的错误检测代码机构和错误恢复机制的冗余存储器系统中提供均匀恢复。错误恢复机制被配置为用于接收故障存储器通道的通知，用于阻止新的操作在存储器通道上启动，以完成存储器通道上的任何未决操作，用于在存储器通道上执行恢复操作并启动至少在存储器通道的第一子集上进行新的操作。存储器系统能够与存储器通道的第一子集一起操作。

67. 发明申请

US20110320864A1 HETEROGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM 有权
标题翻译：冗余存储系统中的异构恢复
公开(公告)号：US20110320864A1
公开(公告)日：2011-12-29
申请号：US12822968
申请日：2010-06-24
申请人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
发明人： Kevin C. Gower , Lisa C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Vesselina K. Papazova , Eldee Stephens
IPC分类号： G06F11/20 , G06F11/08 , G06F11/00
CPC分类号： G06F11/2053 , G06F11/073 , G06F11/0793 , G06F11/1004 , G06F11/108 , G06F11/141 , G06F11/1604 , G06F11/1666 , G06F11/20 , G06F11/2007 , G06F2211/1088
摘要： Providing heterogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for performing a recovery operation on the failing memory channel while other memory channels are performing normal system operations, for bringing the recovered channel back into operational mode with the other memory channels for store operations, for continuing to mark the recovered channel to guard against stale data, for removing any stale data after the recovery operation is complete, and for removing the mark on the recovered channel to allow the normal system operations with all of the memory channels, the removing in response to the removing any stale data being complete.
摘要翻译：在包括存储器控制器，与存储器控制器通信的多个存储器通道，配置用于检测故障存储器通道的错误检测代码机构和错误恢复机制的冗余存储器系统中提供异构恢复。错误恢复机制被配置为用于接收故障存储器通道的通知，用于在其他存储器通道执行正常的系统操作时对故障存储器通道执行恢复操作，以使恢复的通道与其它存储器通道重新进入操作模式，存储操作，用于继续标记恢复的通道以防止陈旧的数据，用于在恢复操作完成之后去除任何陈旧的数据，以及用于去除恢复的通道上的标记，以允许所有存储器通道的正常系统操作，删除，以响应删除任何陈旧的数据完成。

68. 发明授权

US08086783B2 High availability memory system 有权
标题翻译：高可用性内存系统
公开(公告)号：US08086783B2
公开(公告)日：2011-12-27
申请号：US12390731
申请日：2009-02-23
申请人： James A. O'Connor , Kevin C. Gower , Luis A. Lastras-Montano , Warren E. Maule
发明人： James A. O'Connor , Kevin C. Gower , Luis A. Lastras-Montano , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G06F11/1004 , G06F12/0886
摘要： A memory system with high availability is provided. The memory system includes multiple memory channels. Each memory channel includes at least one memory module with memory devices organized as partial ranks coupled to memory device bus segments. Each partial rank includes a subset of the memory devices accessible as a subchannel on a subset of the memory device bus segments. The memory system also includes a memory controller in communication with the multiple memory channels. The memory controller distributes an access request across the memory channels to access a full rank. The full rank includes at least two of the partial ranks on separate memory channels. Partial ranks on a common memory module can be concurrently accessed. The memory modules can use at least one checksum memory device as a dedicated checksum memory device or a shared checksum memory device between at least two of the concurrently accessible partial ranks.
摘要翻译：提供了高可用性的内存系统。存储器系统包括多个存储器通道。每个存储器通道包括至少一个存储器模块，其中存储器件被组织为耦合到存储器设备总线段的部分等级。每个部分等级包括作为存储器设备总线段的子集上的子信道可访问的存储器件的子集。存储器系统还包括与多个存储器通道通信的存储器控制器。存储器控制器通过存储器通道分配访问请求以访问完整等级。完整等级包括在独立内存通道上的至少两个部分等级。可以同时访问公共内存模块上的部分排名。存储器模块可以在至少两个可同时访问的部分等级之间使用至少一个校验和存储器设备作为专用校验和存储器设备或共享校验和存储器设备。

69. 发明申请

US20110228600A1 MEMORY PROGRAMMING 有权
标题翻译：内存编程
公开(公告)号：US20110228600A1
公开(公告)日：2011-09-22
申请号：US13150690
申请日：2011-06-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/21
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

70. 发明申请

US20110138105A1 NON-VOLATILE MEMORIES WITH ENHANCED WRITE PERFORMANCE AND ENDURANCE 有权
标题翻译：具有增强的写性能和耐用性的非易失性存储器
公开(公告)号：US20110138105A1
公开(公告)日：2011-06-09
申请号：US12631505
申请日：2009-12-04
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246
摘要： Enhanced write performance for non-volatile memories including a memory system that includes a receiver for receiving a data rate of a data sequence to be written to a non-volatile flash memory device. The memory system also includes a physical page selector for selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, and for determining if the number of free bits in the invalid previously written memory page at the selected physical address is greater than or equal to the data rate. The memory system also includes a transmitter for outputting the selected physical address of the invalid previously written memory page, the outputting in response to the physical page selector determining that the number of free bits is greater than or equal to the data rate.
摘要翻译：对于非易失性存储器的增强的写入性能，包括存储器系统，该存储器系统包括用于接收要写入非易失性闪速存储器件的数据序列的数据速率的接收器。存储器系统还包括物理页面选择器，用于从位于非易失性存储器设备上的无效的先前写入的存储器页面的一组物理地址中选择无效的先前写入的存储器页面的物理地址，并且用于确定是否有空闲数量在所选物理地址处的无效的先前写入的存储器页中的位大于或等于数据速率。存储器系统还包括用于输出无效的先前写入的存储器页面的所选物理地址的发射器，响应于物理页选择器确定空闲位的数量大于或等于数据速率的输出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式